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參數(shù)資料
| 型號(hào)： | MT90500AL |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR |
| 中文描述： | 多通道自動(dòng)柜員機(jī)AAL1特區(qū) |
| 文件頁(yè)數(shù)： | 71/159頁(yè) |
| 文件大?。?/td> | 514K |
| 代理商： | MT90500AL |
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MT90500
71
the Event Counter, which keeps a running count of the timing reference cells or 8 kHz markers received.
The Cell/8 kHz bit in the Timing Reference Processing Control Register (address 60A0h) is used to
select whether clock recovery is based on Timing Reference Cell arrival events, or 8 kHz marker events.
The Event Count Register (60A2h) is updated every time the CNTUPDATE bit is set HIGH in the Clock
Module General Control Register at 6080h.
a counter which is incremented every eight cycles of CLKx1. The output of this counter is sent to the
Temp Register, which is updated every time the Event Counter is incremented. Finally, the CLKx1 Count
Registers (60A4h and 60A6h) are updated every time the CNTUPDATE bit is set HIGH in the Clock
Module General Control Register at 6080h.
The RXVCLK Clock Generation Block is composed of:
a programmable divider (DIVX Register at address 60A8h) which divides the master IC clock (MCLK) in
order to obtain RXVCLK.
a division factor register (DIVX Ratio Register at address 60AAh) which controls the ratio of divide-by-X
to divide-by-(X+1).
Together, the Adaptive Clock Recovery Block and the RXVCLK Clock Generation Block allow the CPU to
implement an adaptive algorithm which permits the locally generated TDM clock to track the remotely
generated TDM clock.
out of sequence
(except 2nd next)
2nd next sequence
next sequence
previous sequence
next sequence
OUT_OF_
SYNC
IN_SYNC
LOST_CELL
Bad SNP
next sequence
(good SNP)
BAD_SNP
- When going to In_Sync or Bad SNP state, generate one timing reference pulse for each timing
cell received. (“Bad SNP” is bad Sequence Number Protection, meaning a bad CRC, or a bad par-
ity bit.)
- When going to Lost Cell state, generate two timing reference pulses.
- When coming back to In_Sync state from Lost Cell state, generate one pulse if “next sequence”
received. Do not generate pulse if “previous sequence” received, indicating an inverse-ordered
cell condition.
- When in Out_of_Sync state, do not generate timing pulses. If OUT_SYNC_IE bit is set at 6080h,
and TIM_INTE is set at 0000h, an interrupt will be generated on entering Out_Of_Sync.
-
If no timing reference cells or markers have been received within the time-out period set in the
Timing Reference Processing Control Register (60A0h), a Loss of Timing Reference Cells event
will be indicated (LOSS_TIMRF in 6082h), and an interrupt will be generated if LOSSCIE is set at
6080h (and TIM_INTE is set at 0000h).
next sequence
Figure 32 - Timing Reference Cell Processing State Machine
any consecutive error
out of sync (any consecutive
error)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90502 | Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| MT90732AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90732 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90733 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90733AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
| MT90503 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:2048VC AAL1 SAR |
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