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參數(shù)資料
| 型號(hào)： | MT90500AL |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR |
| 中文描述： | 多通道自動(dòng)柜員機(jī)AAL1特區(qū) |
| 文件頁(yè)數(shù)： | 30/159頁(yè) |
| 文件大?。?/td> | 514K |
| 代理商： | MT90500AL |
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MT90500
30
TDM Timing Bus Master - Freerun
(CLKMASTER = ‘1’ in TDM Bus Type Register at 6010h)
In this mode, the MT90500 is configured as the TDM Timing Master and the MT90500 drives the three TDM
bus clocks: CLKx2, CLKx1, and FSYNC. The MT90500 clock generator block uses either the MCLK input or the
PLLCLK input to generate all of the required clocks. Typically in this mode MCLK or PLLCLK is connected to an
oscillator, and no other synchronization source is used. Several selections must be made:
The selection of MCLK or PLLCLK is determined by the BEPLL bits in the Master Clock Genera-
tion Control Register at 6090h.
The selected clock is divided by 1, 2, 4, or 8 to obtain a 16.384 MHz clock, called CLK16. This divi-
sion is controlled by the DIV1...8 bits at 6090h.
TDM Timing Bus Master - 8 kHz Reference
(CLKMASTER = ‘1’ in TDM Bus Type Register at 6010h)
In this mode, the MT90500 is configured as the TDM Timing Master and the MT90500 drives the three TDM
bus clocks, synchronized to one of several possible 8 kHz references. Typically, in this mode, the PLLCLK input
is driven by an external PLL (such as the Mitel MT9041), which is controlled by the REF8KCLK and FREERUN
outputs. The following options are also selectable:
One of four 8 kHz reference sources must be selected, using the REFSEL bits at 6090h. (See
Figure 3 and Section 4.1.1.2 for further details.)
If the external PLL is controlled by the FREERUN output pin, the pin’s operation must be specified
by the FREERUN bits at 6090h. The CPU can force the FREERUN pin to either state, or allow the
FREERUN pin to follow the REF8KCLK failure-detection bit (REFFAIL at 6082h).
Bus Master-Alternate
(CLKMASTER = ‘0’, CLKALT = ‘1’ in TDM Bus Type Register at 6010h)
In this mode, the MT90500 is configured as a TDM Timing Slave, but stands ready to become the Timing
Master, should the timing on the TDM bus fail. The switch is normally automatic (based on the CLKFAIL input),
but can also performed by the CPU (for instance: by programming the chip into TDM Timing Master following a
Clock Absent interrupt). The following options are also selectable:
To make the switch from Alternate to Master automatic, several settings are required: CLKALT at
6010h is set HIGH, and the CORSIGA pin is configured as the CLKFAIL input (CORSIGACNF =
“11” at 6004h).
The Master-Alternate operates normally as a TDM Timing Slave, and has the same options as the
TDM Timing Slave listed above.
The Master-Alternate can be set up to switch to Master-Freerun operation, should the TDM bus
clocks fail. The same options as listed above for Master-Freerun apply to this mode.
The Master-Alternate can be set up to switch to Master-8 kHz Reference operation, should the
TDM bus clocks fail. The same options as listed above for Master-8 kHz Reference apply to this
mode. Additionally, REF8KCLK can be obtained from the TDM bus by dividing CLKx2. This allows
the external PLL to be phase-locked to the TDM bus clocks. Note that in this case the FREERUN
output should be set up to automatically place the external PLL in freerun should the TDM bus
clocks fail.
The internal 8 kHz (FS_INT) of the Master-Alternate can be phase-locked to the TDM bus FSYNC
by setting PHLEN = ‘1’ at 6090h. (This is only valid when the FSYNC type at 6010h is set to “00”.)
This will align the internal “stand-by” FSYNC, CLKx2, and CLKx1 to the TDM bus to within a clock
cycle of the internal 16.384 MHz clock, allowing for minimal phase-shift should the Master-Alter-
nate MT90500 take over the TDM bus clocks.
4.1.1.2
REF8KCLK Selection Logic
The REF8KCLK output pin of the MT90500 is intended to provide a clock reference to an optional external PLL.
This signal would usually be an 8 kHz frame pulse, but other signals are possible. The external PLL (e.g. Mitel
MT9041) can be used to multiply the REF8KCLK output to 16.384 MHz (or 32.768 MHz) and attenuate jitter.
The 16.384 MHz can then be applied to the PLLCLK input pin to allow the MT90500 to generate the TDM
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PDF描述 |
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| MT90733AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
| MT90503 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:2048VC AAL1 SAR |
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