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參數(shù)資料
| 型號(hào)： | MT90500AL |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR |
| 中文描述： | 多通道自動(dòng)柜員機(jī)AAL1特區(qū) |
| 文件頁(yè)數(shù)： | 31/159頁(yè) |
| 文件大小： | 514K |
| 代理商： | MT90500AL |
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MT90500
31
clocks: CLKx2, CLKx1 and FSYNC. The source for the REF8KCLK signal is selected via the REFSEL bits at
address 6090h. The four possible sources for REF8KCLK are:
a clock input signal pin operating at 8 kHz (EX_8KA)
a secondary 8 kHz reference from the TDM bus (SEC8K, compatible with MVIP/H-MVIP)
a freerun mode clock, which is a divided-down version of CLKx2 or MCLK; selected by
DIVCLK_SRC in register 6090h, and divided as specified in register 6092h
RXVCLK, a more precisely divided-down version of MCLK from the Adaptive Clock Recovery
block. The division is controlled by registers 60A8h and 60AAh.
The REF8KCLK signal is made available on the output pin whether the MT90500 is programmed to be TDM
Timing Master or Slave.
Also included in the MT90500 is circuitry to convert the SEC8K signal and the EX_8KA signal into square
waves. If the SEC8K_SQ control bit in register 6090h is set HIGH, internal logic will convert the SEC8K input
signal into a square wave before passing it to the REF8KCLK selection multiplexer. The EX_8KA_SQ bit
controls the squaring function for the EX_8KA signal. See the register 6090h. Mitel PLLs will typically work with
either a pulse 8 kHz, or a square 8 kHz, but other PLL implementations may require a square 8 kHz reference
input.
4.1.1.3
Main TDM Bus Timing and Clock Generation Logic
When the MT90500 is in the TDM Timing Master mode, this logic generates the main TDM bus clocks (CLKx2,
CLKx1, and FSYNC). This block receives CLK16 (a 16.384 MHz clock which is a divided-down version of either
PLLCLK or MCLK, as set in register 6090h) and outputs the generated TDM bus clocks. By programming the
appropriate software registers (i.e. TDMTYP at address 6010h), the generated signals can be 16.384MHz/
8.192MHz/4.096MHz, 8.192MHz/4.096MHz/2.048MHz, and 8 kHz respectively. Additionally, the TDM Bus
Clock Generation Logic generates a source signal to the SEC8K output line when the SEC8KEN register bit is
enabled.
When in TDM Timing Slave mode, or in Master-Alternate mode, this logic generates an internal stand-by 8 kHz
signal (FS_INT), from the clock selected by BEPLL in register 6090h. This can be driven out on SEC8K if
enabled by SEC8KEN.
4.1.1.4
TDM Clock Drivers
If the MT90500 is the TDM Timing Master, this block enables the clock drivers for CLKx2, CLKx1, and FSYNC.
If the MT90500 is in Slave mode, the drivers are disabled and CLKx2, CLKx1, and FSYNC are inputs to the
MT90500. In Slave mode, the CLKx1 source can be separately selected between the CLKx1 input or internally
provided CLKx2/2. These options are controlled by the TDM Bus Type Register at 6010h.
4.1.1.5
Clock Failure Detection
There are three status bits related to the detection of clock failure: REFFAIL (6082h), and CABS and CFAIL
(6002h). These bits will cause an interrupt if their respective enable bits are set (REFFAILIE at 6080h, and
CABSIE and CFAILIE at 6000h) and the TDM_INTE bit is set at 0000h.
The REFFAIL bit monitors the absence of the REF8KCLK signal. When this signal is absent, the clock detect
logic can activate the FREERUN output signal which is used to place the external PLL in freerun mode. Once
the REF8KCLK signal goes back to normal (due to the CPU changing the timing source), the CPU can disable
the FREERUN output signal by clearing the REFFAIL bit in the Clock Module General Status Register at
6082h. With proper selection of the external PLL, this clock failure detection circuit can help to guarantee that
the TDM clocks do not glitch when the REF8KCLK reference to the external PLL changes.
The CABS bit indicates that one or more of the TDM bus clock signals (CLKx2, CLKx1, or FSYNC) are absent.
This block uses MCLK to check for activity on the above signals. In the case of clock absence, the Clock
Absent (CABS) bit in the TDM Interface Status (TIS) Register at address 6002h is activated.
The CFAIL bit monitors the CLKFAIL pin (a SCSA bus signal) and requires that the CORSIGA pin be
configured as the CLKFAIL input. If the CLKFAIL input goes HIGH when the MT90500 is operating in Master-
Alternate mode (CLK_ALT at 6010h), the MT90500 will take over the TDM bus and become the Master TDM
clock source (see the Bus Master-Alternate description in Section 4.1.1).
相關(guān)PDF資料 |
PDF描述 |
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| MT90502 | Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| MT90732AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90732 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
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| MT90733AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
| MT90503 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:2048VC AAL1 SAR |
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