
MT90500
53
PSEL bits are one-hot bits which represent cells with sequence numbers 0, 2, 4, and 6, respectively - see
Table 10 below for an explanation of bit operation). The MT90500 also supports proprietary pointer
transmissions in which a P-byte is sent every 4 cells (PSEL = A hex) or every other cell (PSEL = F hex). Using
these proprietary methods, up to 122 channels can be sent on a particular VC, but this is only possible if the
receiving chip can handle the extra P-bytes during a cycle.
Each “TX Circular Buffer Address” appended to the end of the structure points to a 64-byte circular buffer in
external memory.
Table 10 - Effect of PSEL Field on P-byte Generation
Sequence # 0
Sequence # 2
Sequence # 4
Sequence #6
Applicable Standards
0000
No pointers are sent.
ANSI and ITU-T
- AAL0, AAL5,
pointerless AAL1 Structured
Data Transfer, and partially-
filled cells
1000
Pointer sent.
-
-
-
ANSI and ITU-T
- AAL1-SDT
1010
Pointer sent
-
Pointer sent
-
ANSI
- AAL1-SDT
1111
Pointer sent
Pointer sent
Pointer sent
Pointer sent
ANSI
- AAL1- SDT
8
15
0
7
First Entry field
1 0 0 0 1 1 0
Last Entry field
1 0 0 1 0 0 0
20180
GFC /
VPI(11:8)
Last Entry
First Entry
Payload Size
Current Entry
PSEL
Offset
HEC
TX Circular Buffer Address
V
0
A
AS
SEQ
Circ. Buf. Pnt.
VPI(7:0)
VCI(15:12)
VCI(11:0)
PTI
R S 00
C1
20182
20184
20186
20188
2018A
2018C
TX Circular Buffer Address
V
2018E
First Entry location = 2018C
TX Circular Buffer Address
V
20190
Last Entry location = 20190
A
A
Figure 18 - a: Sample Three-Channel Transmit Control Structure (AAL1/CBR-AAL0)
0
0
8
15
0
7
First Entry field
1 0 0 1 0 0 0
Last Entry field
1 0 0 1 0 0 0
20180
GFC /
VPI(11:8)
Last Entry
First Entry
Payload Size
Current Entry
PSEL
Offset
HEC
0
A
AS
SEQ
Circ. Buf. Pnt.
VPI(7:0)
VCI(15:12)
VCI(11:0)
PTI
R S 00
C1
20182
20184
20186
20188
2018A
2018C
2018E
First Entry location = 20190
TX Circular Buffer Address
V
20190
Last Entry location = 20190
A
A
0
0
Figure 18 - b: Sample One-Channel Transmit Control Structure (CBR-AAL5)
0000 0000 0000 0000
0000 0000 0000 0000