參數(shù)資料
型號： MT90500AL
廠商： Mitel Networks Corporation
英文描述： Multi-Channel ATM AAL1 SAR
中文描述： 多通道自動柜員機AAL1特區(qū)
文件頁數(shù)： 104/159頁
文件大?。?/td> 514K
代理商： MT90500AL
MT90500
104
Table 56 - TX Circular Buffer Base Address Register
Address: 6044(Hex)
Label: TXCBBA
Reset Value: 0000 (Hex)
Label
Bit Position
Type
Description
Reserved
3:0
R/W
Reserved. Should be written as “0000”.
TXCBBASE
15:4
R/W
TX Circular Buffer Base Address. This field represents bits<20:9> of the base address of
the TX Circular Buffer’s base address. The pointer to the circular buffers must not overlap
a 64 Kbyte boundary.
Table 57 - TDM Read Underrun Address Register
Address: 6046 (Hex)
Label: RXUNDA
Reset Value: 0000 (Hex)
Label
Bit Position
Type
Description
TRURTSST
10:0
R/O
TDM Read Underrun Time Slot Stream. Contains the time slot (bits<10:4>) and stream
(bits<3:0>) on which the last underrun was detected.
Reserved
15:11
R/O
Reserved, always read as “0000_0”.
Table 58 - TDM Read Underrun Count Register
Address: 6048 (Hex)
Label: RXUNDC
Reset Value: 0000 (Hex)
Label
Bit Position
Type
Description
TRURCOUNT
15:0
R/O
TDM Read Underrun Counter. Each time a TDM read underrun occurs, this register’s
value is incremented.
Table 59 - Clock Module General Control Register
Address: 6080 (Hex)
Label: CMGCR
Reset Value: 0000 (Hex)
Label
Bit
Position
Type
Description
REFFAILIE
0
R/W
REFFAIL Interrupt Enable - Clock Generation Sub-Module. When enabled, a ‘1’ on
REFFAIL in Register 6082h will force a ‘1’ on TIM_SERV in Register 0002h.
SRTSTSIE
1
R/W
SRTS Transmit Interrupt Enable - SRTS Sub-Module. When enabled, a ‘1’ on
SRTST_UND or SRTST_OVR in Register 6082h will force a ‘1’ on TIM_SERV in Register
0002h.
CNTUPDATE
2
R/W
Counter Update Control - When a ‘1’ is written to this bit, the counts in registers 0x60A2,
0x60A4, and 0x60A6 are updated. The values in those registers will remain the same until
the next time a ‘1’ is written to this bit. The static value of this bit is always ignored.
SRTSRSIE
3
R/W
SRTS Receive Interrupt Enable - SRTS Sub-Module. When enabled, a ‘1’ on SRTSR_UND
or SRTSR_OVR in Register 6082h will force a ‘1’ on TIM_SERV in Register 0002h.
Reserved
4
R/W
Reserved. Should be written as ‘0’.
LOSSCIE
5
R/W
Loss of Timing Reference Cells Interrupt Enable - Timing Reference Cell Sub-Module.
When enabled, a ‘1’ on LOSS_TIMF in Register 6082h will force a ‘1’ on TIM_SERV in
Register 0002h.
相關(guān)PDF資料
PDF描述
MT90502 Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90500AL-ENG1 制造商:Mitel Networks Corporation 功能描述:
MT90502 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR
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MT90502AG 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述:
MT90503 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:2048VC AAL1 SAR
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