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參數(shù)資料
| 型號： | MT90500AL |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR |
| 中文描述： | 多通道自動柜員機AAL1特區(qū) |
| 文件頁數(shù)： | 48/159頁 |
| 文件大?。?/td> | 514K |
| 代理商： | MT90500AL |
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MT90500
48
4.3.2
TX_SAR Process
Figure 19 at the end of this section gives an overview of the processes explained below. A theoretical overview
of scheduler operation is given above, in Section 4.3.1.3.
4.3.2.1
Transmit Event Schedulers
As discussed in Section 4.1.3, a 64-byte Transmit Circular Buffer is maintained in external memory for each
TDM channel whose data needs to be transmitted on the ATM link. Structures known as “transmit event
schedulers” are used to tell the hardware when a cell needs to be assembled for transmission.
The three transmit event schedulers all have similar properties and individual configuration registers. Each
transmit scheduler is divided into a programmable number of “frames”. The circuitry operates to constrain each
scheduler frame to last an average of 125
μ
s, which is the time required for 1 byte to be received / transmitted
on each TDM channel. Within each frame 8, 16, or 32 VC Pointers can be programmed to transmit cells.
When multiple schedulers are used simultaneously, one must assume that any frame in one scheduler can be
superposed onto any frame in another scheduler. To limit cell delay variation, each frame (composed of events
from one, two, or three schedulers) should contain no more than 45 VC Pointers (or transmission events) for
155 Mbps systems, and no more than 7 VC Pointers for 25 Mbps systems. For example, if three schedulers are
programmed and each scheduler’s most-filled frame contains respectively 22, 8, and 28 VC Pointers, the worst
case scenario is a frame with 58 cells, thus over the 45 VC Pointers per frame limit for 155 Mbps. This type of
situation must be avoided to minimize the cell delay variation resulting from an unbalanced or temporarily
overloaded transmit scheduler. The TX_SAR will generate a fatal “SCHEDULE” error (see TX_SAR Status
Register at 2002h) if the schedulers fall behind in their scheduled cell transmission by 8 frames. This would be
caused when more than 8 consecutive frames contain more than 7 (25 Mbps) or 45 (155 Mbps) VC Pointers.
The same error may also occur when the TX_SAR is heavily loaded and other processes are using more
bandwidth than they normally do. The RX_SAR and UTOPIA modules use the external memory’s bandwidth
unevenly over time, depending on the rate at which cells arrive. They can cause “SCHEDULE” errors in the
TX_SAR when the MT90500 is near its maximum load. This error is generated by the TX_SAR when it is at
least 8 frames (1 ms) late.
To prevent cell delay variation, “SCHEDULE” errors, and TDM data unavailability, the software that configures
the TX_SAR should use an efficient algorithm to fill the event schedulers. Events that send cells on the same
VC must be evenly distributed in the event scheduler. The distance between two events associated with the
same VC must be as constant as possible. For an 8-channel AAL1-SDT type cell (with a pointer byte sent in
cell #0 of each sequence), the distance between two events must be 46.975/8 ~ 5.86 frames. Since this
number must be an integer, the event spacing should be 6-6-6-5-6-6-6-5 frames. This regular transmission of
cells is also important in limiting the CDV (Cell Delay Variation) of the transmitted cells.
Each programmable event scheduler is composed of a “base address”, a “short end”, a “l(fā)ong end”, a “l(fā)ong/
short ratio” and a certain number of events per frame, as shown in Figure 15. This information is set in the
TX_SAR registers located at addresses 2010h/2020h/2030h, 2012h/2022h/2032h, and 2014h/2024h/2034h.
The key to supporting different cell types is to have a programmable short and long end for each scheduler. For
AAL1-SDT type cells, the scheduler ends at frame 45 for P-Type cells (short end) and at frame 46 for non P-
Type cells (long end). The ratio between the long and short end can be programmed to either 1 (to generate P-
Type cells every even-numbered cell), 3 (to generate P-Type cells every other even-numbered cell), or 7 (to
generate P-Type cells once in every 8-cell sequence). The PSEL field in the Transmit Control Structure
(Figure 16) must represent the long/short ratio in the event scheduler, except in the case of partially-filled cells.
For a VC which is to carry partially filled cells, the long/short ratio is set to 0.
When the long/short ratio is equal to 0, the scheduler always counts to the long end before returning to frame
0. This mode is used for CBR-AAL0, CBR-AAL5, pointerless AAL1 Structured Data Transfer, and partially-filled
cell formats, since the number of CBR payload bytes in these cells is constant (regardless of the value of the
PSEL field). For a partially filled P-type cell (i.e. containing an AAL1 pointer-byte) one less pad byte is inserted
after the TDM data than for a partially filled cell without a pointer byte. The event scheduler can be truncated
down to as few frames as necessary to support the desired partially-filled cell length. On the other hand, the
event scheduler can also be enlarged so that its length is an integer number which is a multiple of all the partial
length formats that need to be supported. For example a scheduler of length 96 will support the following cell
fill sizes: 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, and 48. For specific examples regarding scheduler configuration,
please refer to the MT90500 Programmers’ Manual.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90502 | Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| MT90732AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90732 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90733 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90733AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
| MT90503 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:2048VC AAL1 SAR |
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