參數(shù)資料
型號: M66596FP
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 0.50 MM PITCH, LQFP-64
文件頁數(shù): 96/133頁
文件大小: 1611K
代理商: M66596FP
M66596FP/WG
rev .1.00
2006.3.14
page 63 of 127
3.2.2
Operation and notes in a clock stop state
VBINT
, RESM, and BCHG generate a interrupt status in the clock stop(include low-power sleep state) . When
clearing the interrupt status VBINT, RESM, and BCHG in the clock stop state, it is necessary to write "0" in the bit of
an interrupt status register, then to write in "1" further.
3.2.3
BRDY interrupt
The BRDY interruption is generated whichever it has chosen of Host and Peripheral mode.
Table 3.9 shows the conditions under which the controller sets “1” to a pertinent bit of the BRDYSTS register.
Under above condition, the controller generats BRDY interrupt, if software enables PIPERDYE bit of the BRDYENB
register and BRDYE bit of the INTENB0 register. Figure 3.13 shows the timing at which BRDY interrupts are
generated..
The conditions for elimination the BRDY bit of the INTSTS0 register are depend on the setting of the BRDYM bit of
the INTENB1 register. Table 3.10 shows the conditions.
Under the conditions noted below in the Peripheral mode, a Zero-Length packet is sent for an IN token, and the
BRDY
interrupt is not generated.
- When “0x000” is set in the MXPS bit of the PIPEMAXP register for a pipe, and the transfer type of the pertinent
pipe is bulk IN.
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