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參數(shù)資料
| 型號： | M66596FP |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 0.50 MM PITCH, LQFP-64 |
| 文件頁數(shù)： | 115/133頁 |
| 文件大小： | 1611K |
| 代理商： | M66596FP |
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M66596FP/WG
rev .1.00
2006.3.14
page 80 of 127
3.4.2
FIFO port functions
Table 3.16 shows the settings for the FIFO port functions of the controller. When data writing is being
accessed, writing data until the buffer is full (or the maximum packet size for non-continuous transfers)
automatically enables sending of the data. To enable sending of data before the buffer is full (or before the
maximum packet size for non-continuous transfers), the BVAL bit of the C/DxFIFOCTR register (or the DEND
signal when using DMA transfers) must be set to end the writing. Also, to send a Zero-Length packet, the BCLR
bit of the same register must be used to clear the buffer and then the BVAL bit set in order to end the writing.
When accessing reading, reception of new packets is automatically enabled if all of the data has been read.
However, data cannot be read when a Zero-Length packet is being received (DTLN=0), so the BCLR bit of the
register must be used to releasethe buffer. The length of the data being received can be confirmed using the
DTLN
bit of the C/DxFIFOCTR register.
Table 3.16 FIFO port function settings
Register name
Bit name
Function
Reference
Note
REW
Buffer memory rewind (re-read, re-write)
DCLRM
Automatically clears data received for a specified
pipe after the data has been read
For DxFIFO
only
DMA transfer
assumed
DREQE
Asserts DREQ signal
For DxFIFO
only
MBW
FIFO port access bit width
TRENB
Enables transaction counter operation
For DxFIFO
only
TRCLR
Clears the current number of transactions
For DxFIFO
only
DEZPM
Zero-Length packet addition mode
For DMA only
C/DxFIFOSEL
ISEL
FIFO port access direction
For DCP only
BVAL
Ends writing to the buffer memory
BCLR
Clears the buffer memory on the CPU side
C/DxFIFOCTR
DTLN
Confirms the length of received data
DxFIFOTRN
TRNCNT
Sets the received transaction count
For DxFIFO
only
TGL
CPU / SIE buffer toggle
For CFIFO only
CFIFOSIE
(excluding
DCP)
SCLR
Clears the buffer memory on the SIE side
For CFIFO only
External pin
DEND
Ends writing to the buffer memory
For DMA
transfer only
3.4.2.1 FIFO port selection
Table 3.17 shows the pipes that can be selected with the various FIFO ports. The pipe to be accessed is
selected using the CURPIPE bit of the C/DxFIFOSEL register. After the pipe has been selected, “FRDY=1” should
be confirmed before accessing the FIFO port.
Also, the bus width to be accessed should be selected using the MBW bit. The buffer memory access direction
conforms to the DIR bit of the PIPExCFG register. However, the ISEL bit determines this only for the DCP.
Table 3.17 FIFO port access categorized by pipe
Pipe
Access method
Port that can be used
DCP
CPU access
CFIFO port register
CPU access
CFIFO port register
DxFIFO port register
PIPE1~PIPE7
DMA access
DxFIFO port register
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相關代理商/技術參數(shù) |
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| M66596FP#RB0Z | 制造商:Renesas Electronics Corporation 功能描述:MCU - Trays 制造商:Renesas Electronics 功能描述:USB Device Controller 64-Pin LQFP Cut Tape 制造商:Renesas Electronics 功能描述:USB Device Controller 64-Pin LQFP Tray 制造商:Renesas 功能描述:USB Device Controller 64-Pin LQFP |
| M66596FPRB0Z | 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Dual Function Controller,LQFP64 |
| M66596WG | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:ASSP (USB2.0 Dual Function Controller) |
| M66596WG#RB0Z | 制造商:Renesas Electronics 功能描述:Tray 制造商:Renesas 功能描述:0 |
| M6668 | 制造商:Tamura Corporation of America 功能描述: |
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