參數(shù)資料
型號: M66596FP
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 0.50 MM PITCH, LQFP-64
文件頁數(shù): 89/133頁
文件大?。?/td> 1611K
代理商: M66596FP
M66596FP/WG
rev .1.00
2006.3.14
page 57 of 127
3.1.8.3 Starting the internal clock supply (from the low-power sleep state to the normal operating state:
Auto clock supply function enabled)
Figure 3.7 shows a diagram of the timing at which the transition from the low-power sleep state to the normal
operating state takes place when the auto clock supply function is enabled (“ATCKM=1”). When the auto clock
supply function is enabled, the controller carries out register control, so after an interrupt is generated, the
transition to the normal operating state is completed simply by waiting for the amount of time that access is disabled.
No operation of the registers using the softwear is necessary.
In the Peripheral mode when operation has been resumed from the suspended state using the USB Bus Reset
signal, it is necessary to recover to the normal operating state within 3 ms after the data line change has been
detected so that the controller can begin the reset handshake protocol. When the auto clock supply function is
enabled, the controller waits automatically for oscillation to stabilize and then carries out clock supply control and
handles the reset handshake. Because there is a signal output time of 10 ms for the USB Bus Reset signal and of 20
ms for the Resume signal, the control program is provided with plenty of allowance to process the recovery to the
normal state.
The recovery sequence when the auto clock supply function is enabled is as shown below.
(1)
An interrupt is generated to recover from the low-power sleep state, and the INT_N pin is asserted.
(Or, the control program writes dummy data to the 0x7E address to cause the controller to recover.)
(2)
At the same time, the controller automatically enables the oscillation buffer. "XCKE=1(H/W)"
(3)
The softwear directs the system to wait until access is enabled. (A waiting time of at least 2.5 ms is
necessary.)
(4)
The controller automatically enables RCKE, PLLC, and SCKE.
(5)
The softwear resets the registers that have been in the held state before going into the low-power sleep state.
*1) In the Peripheral mode when the system has recovered from the low-power sleep state to the normal operating
state, the USB communication speed and the device state recovery settings have to be set in the STSRECOV bit
of the RECOVER register, and the USB address in the USBADDR bit of that register, for recovery to take place.
If the auto clock supply function has been enabled, however, the recovery settings for the above bits should be
entered after the DVSQ bit has been confirmed. This is because, if recovery has been made using the USB Bus
Reset signal, there is a possibility that the controller has initialized the device state and the USB address to the
default state, in which case rewriting the register values to the waiting state will cause erroneous operation.
The recovery settings are written to the RECOVER register using the procedure outlined below.
-
If “DVSQ=000”, recovery is made by a method other than the USB Bus Reset signal. The USB
communication speed, device state, and USB address should be returned to the state they were in prior to
shifting to the low-power sleep state, by writing to the RECOVER register.
-
If “DVSQ=001”, recovery is made using the USB Bus Reset signal. The recovery settings should not be
entered by writing to the RECOVER register.
Also, in the low-power sleep state, there are registers that are initialized by the controller. When recovery has
been made to the normal operating state, the initialized registers should be reset to match the user system.
XCKE(H/W )
RCKE(H/W)
PLLC(H/W)
SCKE(H/W )
(3)2.5ms (access disabled)
Low-power sleep
state recovery
PCUT(H/W)
INT_N
Event
CS_N
(1),(2)
(4)
Figure 3.7 Recovery control timing from the low-power sleep state with “ATCKM=1”
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