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參數(shù)資料
| 型號： | HSP50210JI-52 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Digital Costas Loop |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQCC84 |
| 封裝： | PLASTIC, MS-018AFA, LCC-84 |
| 文件頁數(shù)： | 8/49頁 |
| 文件大?。?/td> | 326K |
| 代理商： | HSP50210JI-52 |
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3-260
The I&D filter consists of an accumulator, a programmable
shifter and a two sample summer as shown in Figure 3. The
programmable shifter is provided to compensate for the gain
introduced by the accumulator (see Table 14). The
accumulator provides Integrate and Dump Filtering for
decimation factors up to 16. The two sample summer
provides the moving average required for an additional
decimation factor of 2. A decimation factor of 1 (bypass), 2,
4, 8, 16, or 32 may be selected. At the maximum decimation
rate, a baseband signal sampled at 32 times the symbol rate
can be filtered.
The output of the two sample summer is demultiplexed into
two sample streams at the symbol rate. The demultiplexed
data streams from the I and Q processing paths are fed to
the Symbol Tracking Block and Soft decision slicer. The
multiplexed data streams on I and Q are provided as one of
the selectable inputs for the Cartesian to Polar Converter.
Cartesian/Polar Converter
The Cartesian/Polar Converter maps samples on the I and Q
processing paths to their equivalent phase/magnitude
representation. The magnitude conversion is equivalent to:
where 0.81 is the gain of the conversion process. The
magnitude output is an 8-bit unsigned value ranging from 0.0
to 1.9922.
0
-20
-40
-60
-80
-100
0
f
CLK
10
FREQUENCY (NORMALIZED TO INPUT SAMPLE RATE)
N
FIGURE 4. RRC FILTER IN HSP50210
2f
CLK
10
3f
CLK
10
4f
CLK
10
f
CLK
2
0
-0.18
-0.36
-0.54
-0.72
-0.90
0
-0.07
-0.14
-0.21
-0.28
-0.35
0
FREQUENCY (NORMALIZED TO INPUT SAMPLE RATE)
f
CLK
25
2f
CLK
25
3f
CLK
25
4f
CLK
25
f
CLK
5
FIGURE 5. PASSBAND RIPPLE OF RRC FILTER IN HSP50210
N
N
SHOWN BELOW
ENLARGED FOR CLARITY
0
f
CLK
40
f
CLK
20
3f
CLK
40
f
CLK
10
3f
CLK
20
5f
CLK
40
TABLE 1. ROOT RAISED COSINE COEFFICIENTS
COEFFICIENT INDEX
COEFFICIENT
0
2
1
-2
2
1
3
8
4
-16
5
-14
6
86
7
160
8
86
9
-14
10
-16
11
8
12
1
13
-2
14
2
Mag (I, Q)
0.81
(
)
I
2
Q
2
+
(
)
,
=
(EQ. 5)
HSP50210
相關PDF資料 |
PDF描述 |
|---|---|
| HSP50210JC-52 | Digital Costas Loop |
| HSP50216KI | Four-Channel Programmable Digital DownConverter |
| HSP50307SC | Burst QPSK Modulator |
| HSP50307EVAL1 | 2.0GHz to 2.7GHz DownConverter |
| HSP50415 | Wideband Programmable Modulator(寬帶可編程調(diào)制器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50210JI-52Z | 功能描述:上下轉(zhuǎn)換器 COSTAS DEMODULATOR 84 PLCC 52MHZ IND RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50214 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214AVC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50214AVI | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
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