參數資料
型號： HSP50210JI-52
廠商： INTERSIL CORP
元件分類： 通信及網絡
英文描述： Digital Costas Loop
中文描述： SPECIALTY TELECOM CIRCUIT, PQCC84
封裝： PLASTIC, MS-018AFA, LCC-84
文件頁數： 41/49頁
文件大?。?/td> 326K
代理商： HSP50210JI-52
3-293
TABLE 38. HALT LOCK DETECTOR FOR READING CONTROL REGISTER
DESTINATION ADDRESS = 24
BIT
POSITION
FUNCTION
DESCRIPTION
N/A
Stop Lock Detector for
Reading
Writing this location halts the Lock Detector State Machine at the end of the current Lock Detector
Accumulator integration cycle. This function is provided so that the Lock Detector integrators can be
stopped for reading via the microprocessor interface (only useful when the Lock Detector is under
internal state machine control). Bit 7 of the internal status register can be monitored via the
Microprocessor Interface to determine when the Lock Detector has stopped and is ready for reading.
See Table 13 for information on the internal status bits. The Lock Detector will remain stopped until
restarted (see Restart Lock Detector Control Register: Table 39).
TABLE 39. RESTART LOCK DETECTOR CONTROL REGISTER
DESTINATION ADDRESS = 25
BIT
POSITION
FUNCTION
DESCRIPTION
N/A
Restart Lock Detector
Writing this location restarts the Lock Detector State Machine following a read of the Lock Detector.
Note:
Stopping the Lock Detector for reading is not required in Microprocessor Control Mode since the
Lock Detector Accumulators stop at the end of each integration cycle.
See also Table 44.
TABLE 40. SOFT DECISION SLICER CONFIGURATION CONTROL REGISTER
DESTINATION ADDRESS = 26
BIT
POSITION
FUNCTION
DESCRIPTION
31-8
Not Used
No programming required.
7
Slicer Output Format
0 = Soft decision outputs are in sign/magnitude format.
1 = Soft decision outputs are in two’s complement format.
6-0
Soft Decision
Threshold
The input to the slicer is compared against thresholds which are 1x, 2x and 3x the value programmed
here. The slicer output depends on the relationship of the I or Q magnitude to the 3 soft thresholds as
given in Table 7. The threshold is programmed as a fractional unsigned value with the following bit
weightings:
0. 2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.
Note: Since the signal magnitude on either the I or Q path ranges between 0.0 and
~
1.0, the
threshold value should not exceed 1.0/3 = 0.33. Bit position 6 is the MSB.
TABLE 41. SERIAL OUTPUT CONFIGURATION CONTROL REGISTER
DESTINATION ADDRESS = 27
BIT
POSITION
FUNCTION
DESCRIPTION
31-16
Not Used
No programming required.
15-13
Reserved
Set to zero for proper operation.
12
Serial Data Sync
Polarity
(SOF output)
0 = SOFSYNC pulses “High” one serial clock before data word on SOF.
1 = SOFSYNC pulses “Low” one serial clock before data word on SOF.
Set to 0 for use with the HSP50110.
11
Serial Data Sync
Polarity
(COF output)
0 = COFSYNC pulses “High” one serial clock before data word on COF.
1 = COFSYNC pulses “Low” one serial clock before data word on COF.
Set to 0 for use with the HSP50110.
HSP50210
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