參數(shù)資料
型號(hào): HSP50210JI-52
廠商: INTERSIL CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Digital Costas Loop
中文描述: SPECIALTY TELECOM CIRCUIT, PQCC84
封裝: PLASTIC, MS-018AFA, LCC-84
文件頁(yè)數(shù): 28/49頁(yè)
文件大?。?/td> 326K
代理商: HSP50210JI-52
3-280
WR
CLK
A0-2
C0-7
NOTE:
that the processor waveforms meet the parameters in the Waveforms Section of this data sheet to ensure proper operation. The Processor wave-
forms are not required to be synchronous to CLK. They are shown that way to clarify the illustration.
These processor signals are meant to be representative. The actual shape of the waveforms will be set by the microprocessor used. Verify
FIGURE 21. CONTROL REGISTER LOADING SEQUENCE
1
2
3
4
EARLIEST TIME ANOTHER
LOAD CAN BEGIN
4
3
2
1
0
0
1
DON’T CARE
RD
P
S
NOTE:
that the processor waveforms meet the parameters in the Waveforms Section of this data sheet to ensure proper operation. The Processor wave-
forms are not required to be synchronous to CLK. They are shown that way to clarify the illustration.
Load the Write Address Register with 29
dec
to load the output holding registers.
Enable Carrier Loop Filter Lag Accumulator holding register for reading.
2
These processor signals are meant to be representative. The actual shape of the waveforms will be set by the microprocessor used. Verify
Select the MSByte of the output holding register for output.
Assert RD low to output data on C0-7. (Must wait for 6 CLKs after loading the holding registers).
Select other bytes of holding register by changing A0-2 and asserting RD.
FIGURE 22. LOOP FILTER ACCUMULATOR READ SEQUENCE
1
3
4
5
WR
CLK
A0-2
C0-7
1
2
3
4
3
1
5
4
0
2
DON’T CARE
RD
P
S
1
2
3
4
5
MSB
LSB
0
29
5
6
LOAD OUTPUT
HOLDING REG
WAIT
6 CLKs
ENABLE
HOLDING
REG
FOR
READ
DELAY
TO
RD
ASSERT
READ
READ
READ
READ
ADDRESS IS ASYNCHRONOUS TO CLK
DATA IS
ASYNCHRONOUS
TO CLK
HSP50210
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