參數(shù)資料
型號: HSP50210JI-52
廠商: INTERSIL CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Digital Costas Loop
中文描述: SPECIALTY TELECOM CIRCUIT, PQCC84
封裝: PLASTIC, MS-018AFA, LCC-84
文件頁數(shù): 37/49頁
文件大?。?/td> 326K
代理商: HSP50210JI-52
3-289
8
Single/Double Rail
Sampling Error
This bit sets whether sampling error is derived from symbol transitions on just the I rail (single rail) or both
the I&Q rails (dual rail). In single rail operation sampling error from the Q rail is nulled and only the I rail is
used. In dual rail operation the sampling error from both the I an Q rails is summed and then scaled by one
half.
0 = Dual Rail Operation.
1 = Single Rail Operation.
Note: Set to 1 for BPSK operation and 0 for QPSK operation.
7-3
Sampling Error
Accumulation
These bits set the number of sampling error measurements to accumulate before running the Symbol Loop
Filter. The loop filter requires 8 CLKs to compute an output. The sampling error detector generates error
terms at the symbol rate. Thus, the error accumulator must be used if the symbol rate exceeds 1/8 CLK to
ensure that no error terms are missed (see Sampling Error Detector Section). The 5-bit value programmed
here is set to one less than the desired number of error terms to accumulate. For example, setting these
bits to 00011 (BINARY) would cause 4 error terms to be accumulated. A total range from 1 to 32 is provided.
2
Lead Sampling Error
Enable
0 = Sampling error enabled to lead path of loop filter.
1 = Sampling error to lead path of loop filter zeroed.
1
Lag Sampling Error
Enable
0 = Sampling error enabled to lag path of loop filter.
1 = Sampling error to lag path of loop filter zeroed (First Order Loop).
0
Invert Sampling Error
0 = Sampling error normal.
1 = Sampling error inverted.
TABLE 29. SYMBOL TRACKING LOOP FILTER UPPER LIMIT CONTROL REGISTER
DESTINATION ADDRESS = 15
BIT
POSITION
FUNCTION
DESCRIPTION
31-0
Symbol Tracking
Loop Filter Upper
Limit
The 32-bit two’s complement value programmed here sets the upper tracking limit of the Symbol Tracking Loop
Filterbysettingtheupperlimitof theloop filter’slag accumulator.Ifthe limitisexceeded, theupper32bitsofthe
40-bit accumulator are set to the limit, and the 8 LSBs are set to zero.
TABLE 30. SYMBOL TRACKING LOOP FILTER LOWER LIMIT CONTROL REGISTER
DESTINATION ADDRESS = 16
BIT
POSITION
FUNCTION
DESCRIPTION
31-0
Symbol Tracking
Loop Filter Lower
Limit
The 32-bit two’s complement value programmed here sets the Lower tracking limit of the Symbol Tracking Loop
Filter by setting the lower limit of the loop filter’s lag accumulator. If the running sum falls below the limit, the upper
32 bits of the 40-bit accumulator are set to the limit, and the 8 LSBs are set to zero.
TABLE 31. SYMBOL TRACKING LOOP FILTER GAIN (ACQ) CONTROL REGISTER
DESTINATION ADDRESS = 17
BIT
POSITION
FUNCTION
DESCRIPTION
31-24
Not Used
No programming required.
23-18
Reserved
Reserved. Set to 0 for proper operation.
17-14
Symbol Tracking
Lead Gain Mantissa
(Acquisition)
These bits are the 4 fractional bits of the lead gain mantissa shown below:
Symbol Tracking Lead Gain Mantissa = 01. 2
-1
2
-2
2
-3
2
-4.
This format provides a mantissa range from 1.0 to 1.9375 for mantissa settings from 0000 to 1111 Binary.
Bit position 17 is the MSB.
TABLE 28. SYMBOL TRACKING LOOP CONFIGURATION CONTROL REGISTER (Continued)
DESTINATION ADDRESS = 14
BIT
POSITION
FUNCTION
DESCRIPTION
HSP50210
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