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參數資料
| 型號： | HSP50210JI-52 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | Digital Costas Loop |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQCC84 |
| 封裝： | PLASTIC, MS-018AFA, LCC-84 |
| 文件頁數： | 13/49頁 |
| 文件大?。?/td> | 326K |
| 代理商： | HSP50210JI-52 |
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Loop Gain and potentially, the AGC limits. The maximum AGC
response is the maximum gain adjustment made in any given
clock cycle. This involves applying maximum Loop gain and
setting the AGC limits as wide as possible. A calculation using
only exponent terms of the various gains will be sufficient to
yield a rough order of magnitude of the range of the AGC
Loop response. The results are shaded in the last column of
Table 6 and provided in detail in Equations 9A and 9B.
AGC Response
MAX
= Input (Cartesian to Polar Converter Gain)(Error Detector Gain)(AGC Loop Gain)(AGC Output Weighting)
AGC Response
MAX
=
±
1(0.5)(0.5)(2
-7
)(24) =
±
1(2
-9
)(24) = 0.04688dB/symbol time
where (0.5) is the MSB of the 0.81 scaling in the Cartesian to Polar Coordinate Converter, (0.5) is the MSB of the mantissa of the
Loop Gain, (2
-7
) is the maximum shift gain, and 24 is the maximum loop filter gain.
A similar procedure is used to calculate the minimum AGC response rate.
AGC Response
MIN
=
±
1(0.5)(0.5)(2
-14
)(24) =
±
1(2
-16
)(24) = 0.000366dB/symbol time
Thus, the expected range for the AGC rate is approximately 0.0004 to 0.0469dB/symbol time.
TABLE 6. AGC BIT WEIGHTING
AGC
ACCUM
BIT
POSITION
GAIN
ERROR
INPUT
GAIN
ERROR
BIT
WEIGHT
AGC LOOP
FILTER GAIN
(MANTISSA)
AGC LOOP
FILTER
GAIN
MULIPLIER
(OUTPUT)
AGC
LOOP
FILTER
GAIN BITS
KEPT
(rnd)
SHIFT
= 0
SHIFT
= 7
AGC
OUTPUT
AND AGC
LIMITS BIT
WEIGHT
AGC GAIN
RESOLUTION
(dB)
22
Shifter
→
E
Shifter
→
E
1
12
21
0
6
20
Multiplier
→
M
-1
3
19
M
-2
1.5
18
M
-3
0.75
17
M
-4
0.375
16
M
-5
0.1875
15
Multiplier
→
1
M
-6
0.09375
14
13
1
G
-8
0.02344
12
2
G
-9
0.01172
11
3
G
-10
0.00586
10
4
G
-11
0.00293
9
5
G
-12
0.00146
8
8(S)
= 1(S)
0.
12(S)
12(S)
= 1
1
6
G
-13
0.000732
7
7
= 0
x
11
11
= 0
6
6
= 1
x
10
10
= 1
1
G
-15
0.000183
5
5
= 2
x
9
9
= 2
2
G
-16
0.0000916
4
4
= 3
x
8
8
= 3
3
G
-17
0.0000458
3
3
= 4
7
7
= 4
4
G
-18
0.0000229
2
2
= 5
6
6
= 5
5
-19
0.0000114
1
1
= 6
5
5
= 6
6
-20
0.00000572
0
0
= 7
4
-21
0.00000286
3
2
1
0
0
0-7
0.04688
0
G
-14
0.000366
(EQ. 9A)
(EQ. 9B)
HSP50210
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PDF描述 |
|---|---|
| HSP50210JC-52 | Digital Costas Loop |
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| HSP50307SC | Burst QPSK Modulator |
| HSP50307EVAL1 | 2.0GHz to 2.7GHz DownConverter |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| HSP50210JI-52Z | 功能描述:上下轉換器 COSTAS DEMODULATOR 84 PLCC 52MHZ IND RoHS:否 制造商:Texas Instruments 產品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50214 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214AVC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50214AVI | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
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