參數(shù)資料
型號: HSP50210JI-52
廠商: INTERSIL CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Digital Costas Loop
中文描述: SPECIALTY TELECOM CIRCUIT, PQCC84
封裝: PLASTIC, MS-018AFA, LCC-84
文件頁數(shù): 42/49頁
文件大小: 326K
代理商: HSP50210JI-52
3-294
10
Serial Clock Phase
Relative to Data
0 = Rising edge of serial clock at center of data bit.
1 = Falling edge of serial clock at center of data bit. Set to 0 for use with the HSP50110.
9-8
Serial Clock Divider
These bits set the clock rate of SLOCLK.
00 -> SLOCLK = CLK/2.
01 -> SLOCLK = CLK/4.
10 -> SLOCLK = CLK/8.
11 -> SLOCLK = CLK/16.
7
Serial Clock Select for
COF Output
0 = CLK is used as the serial clock.
1 = SLOCLK is used as the serial clock.
Note: If the HSP50210 is used together with the HSP50110, CLK must be selected as the serial
clock for the SOF and COF outputs, and the same CLK must be used by both chips.
6-4
Serial Word Length for
COF Output
000 = 8 Bits
001 = 12 Bits
010 = 16 Bits
011 = 20 Bits
100 = 24 Bits
101 = 28 Bits
110 = 32 Bits
111 = 40 Bits
3
Serial Clock Select for
SOF Output
0 = CLK is used as the serial clock.
1 = SLOCLK is used as the serial clock.
Note: If the HSP50210 is used together with the HSP50110, CLK must be selected as the serial
clock for the SOF and COF outputs, and the same CLK must be used by both chips.
2-0
Serial Word Length for
SOF Output
000 = 8 Bits
001 = 12 Bits
010 = 16 Bits
011 = 20 Bits
100 = 24 Bits
101 = 28 Bits
110 = 32 Bits
111 = 40 Bits
TABLE 41. SERIAL OUTPUT CONFIGURATION CONTROL REGISTER (Continued)
DESTINATION ADDRESS = 27
BIT
POSITION
FUNCTION
DESCRIPTION
HSP50210
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