參數(shù)資料
型號(hào)： HSP50210JI-52
廠商： INTERSIL CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Digital Costas Loop
中文描述： SPECIALTY TELECOM CIRCUIT, PQCC84
封裝： PLASTIC, MS-018AFA, LCC-84
文件頁(yè)數(shù)： 33/49頁(yè)
文件大小： 326K
代理商： HSP50210JI-52
3-285
5-2
Phase Offset
These bits set the phase offset added (modulo 2
π
) to the phase output of the Cartesian to Polar
Converter. The phase offset is represented as a 4-bit fractional 2’s Complement value with the following
binary format:
Phase Offset = -2
0
. 2
-1
2
-2
2
-3.
This format provides a range from 0.875 to -1 (0111 to 1000) which corresponds to phase offset settings
from 7
π
/8 to -
π
respectively. Resolution of 22.5
o
is provided. Bit position 5 is the MSB.
1-0
Shift Factor
The bits set the left shift required by the Carrier Phase Error Detector. These two bits specify a left shift
of 0, 1, 2 or 3 places. MSBs are discarded and LSBs are zero-filled. Bit 1 is the MSB.
TABLE 17. CARRIER PHASE ERROR DETECTOR CONTROL REGISTER (Continued)
DESTINATION ADDRESS = 3
BIT
POSITION
FUNCTION
DESCRIPTION
TABLE 18. FREQUENCY DETECTOR CONTROL REGISTER
DESTINATION ADDRESS = 4
BIT
POSITION
FUNCTION
DESCRIPTION
31-8
Not Used
No programming required.
7-3
Reserved
Reserved. Set to 0 for proper operation.
2-0
Discriminator Delay
The frequency detector (discriminator) computes frequency by subtracting a delayed phase term from
the current phase term (d
θ
/dt). A programmable delay is used to set the discriminator gain. These bits
set the delay as given by:
Delay = 2
K
,
where K is the 3-bit value programmed here. Delays of 1, 2, 4, 8, and 16 are possible.
TABLE 19. FREQUENCY ERROR DETECTOR CONTROL REGISTER
DESTINATION ADDRESS = 5
BIT
POSITION
FUNCTION
DESCRIPTION
31-8
Not Used
No programming required.
7-3
Frequency Offset
These bits set the frequency offset added (modulo) to the frequency output of the discriminator. The frequency
offset is represented as a 5-bit fractional 2’s complement value with the following binary format:
Frequency Offset = -2
0
. 2
-1
2
-2
2
-3
2
-4.
This format provides a range from 0.9375 to -1.0 (0111 to 1000). The range and resolution of the
frequency offset depend on the discriminator delay and input rate. The frequency offset is added to the
5 MSBs of the discriminator output. Note: Set the frequency offset to 0 when using frequency aided
acquisition with PSK waveforms.
2-0
Shift Factor
These bits set the left shift required by the Frequency Error Detector. These two bits set a left shift of 0,
1, 2, 3, or 4 places. Bit 2 is the MSB. Values greater than 4 are invalid.
Note: Set the shift factor to 0
when using frequency aided acquisition with PSK waveforms.
TABLE 20. CARRIER LOOP FILTER CONTROL REGISTER #1
DESTINATION ADDRESS = 6
BIT
POSITION
FUNCTION
DESCRIPTION
31-8
Not Used
No programming required.
7
Reserved
Reserved. Set to 0 for proper operation.
6
Lead/Lag to Serial
Output Routing
0 = The Carrier Loop Filter’s Lag Accumulator is routed to the Serial Output Controller.
1 = The lead and lag paths in the Carrier Loop Filter are summed and routed to the Serial Output
Controller.
5
Lead/Lag to Internal
NCO Routing
0 = Sum of lead and lag paths routed to the internal NCO. (32 MSBs of sum are routed).
1 = The lead term is routed to the internal NCO. (32 MSBs of lead term are routed).
HSP50210
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