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參數(shù)資料
| 型號： | HSP50210JI-52 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Digital Costas Loop |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQCC84 |
| 封裝： | PLASTIC, MS-018AFA, LCC-84 |
| 文件頁數(shù)： | 14/49頁 |
| 文件大小： | 326K |
| 代理商： | HSP50210JI-52 |
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3-266
Gain Distribution
The gain distribution in the DCL is shown in Figure 10.
These gains consist of a combination of fixed,
programmable, and adaptive gains. The fixed gains are
introduced by processing elements such as the Mixer and
Square Root of Root Raised Cosine Filter. The adaptive
gains are set to compensate for variations in input signal
strength.
The main signal path, with processing block gains and path
bit weightings, is shown in Figure 10. The quadrature inputs
to the HSP50210 are 10-bit fractional two’s complement
numbers with relative bit weightings, as shown in the
Figure 10. The first element in the processing chain is the
Mixer, which scales the quadrature outputs of the complex
multiplier by 1/2 providing a gain of G = 0.5. If the Mixer is
bypassed, the signal is passed unmodified with a gain of 1.0.
Following the mixer, the quadrature signal is passed to the
fixed coefficient RRC filtering block, which has a gain of 1.13
if enabled and 1.0 if bypassed. Next, the AGC supplies gain
to maintain an optimal signal level at the input to the Soft
Decision Slicer, Cartesian to Polar Converter, and the
Symbol Tracking Loop. The gain supplied by the AGC
ranges from 1.0 to 1.9844*2
3
.
Following the AGC, the signal path is limited to 8 bits and
passed through the Integrate and Dump Filter en route to the
Soft Decision Slicer and Symbol Tracking Block.The I&D Filter
uses an accumulator together with a sample pair summer to
achieve the desired decimation rate. The I&D shifter is
provided to compensate for the gain introduced by the I&D
Accumulator. The accumulator introduces gain equal to the
decimation factor R, and the shifter gain can be set to 1/R. For
example, if the I&D Filter decimation of 16 is chosen the I&D
Accumulator will accumulate 8 samples before dumping,
which produces a gain of 8. Thus, for unity gain, the I&D
Shifter would be set for a gain of 2
-3
. The Sample Pair
Summer is unity gain since its output is scaled by one-half.
Symbol Tracking
The symbol tracking loop adjusts the baseband sampling
frequency to force sampling of the baseband waveform at
optimal points for data decisions. The key elements of this
loop are the Sampling Error Detector and Symbol Tracking
Loop Filter shown in Figure 11. The output of these two blocks
is a frequency correction term which is used to adjust the
baseband sample frequency external to the HSP50210. In
typical applications, the frequency correction term is fed back
to the HSP50110 to adjust baseband sampling via the
Resampling NCO (see HSP50110 Datasheet).
SYNTHESIZER/
MIXER
G = 1.0, 0.5 (NOTE 1)
-2
0
2
-9
2
-1
MANTISSA
1.0 - 1.9844
(0.0156 STEPS)
EXPONENT
2
0
-2
3
G = 1.0 - 1.9844*2
3
L
I
M
I
T
SAMPLE PAIR
SUMMER
BINARY
POINT
AGC GAIN
PART
INPUT
RRC
FILTER
G = 1.0, 1.13 (NOTE 2)
-2
0
2
0
2
-10
2
-1
-2
1
RND
2
-10
RND
2
-1
2
0
2
-9
2
-1
2
1
2
2
2
3
2
4
-2
5
-2
0
2
-7
RND
2
-1
INT/DUMP
ACCUMULATOR
G = 1-16
2
-7
2
-1
2
0
2
1
2
2
2
3
-2
4
INT/DUMP
SHIFTER
G = 2
0
- 2
-4
2
-11
2
-1
2
0
2
1
2
2
2
3
-2
4
-2
0
2
-6
2
-1
-2
0
2
-6
2
-7
2
-1
G = 0.5, 1.0 (NOTE 3)
INPUT TO
SOFT DECISION
SLICER
AND
SYMBOL TRACKING
BLOCK
INPUT TO CARTESIAN TO POLAR CONVERTER
IF AGC OUTPUT SELECTED
INPUT TO CARTESIAN TO POLAR CONVERTER
IF INT/DUMP OUTPUT SELECTED
INTEGRATE AND
DUMP FILTER
L
I
M
I
T
NOTES:
1. If the Mixer is enabled the result of the complex multiply is scaled by two (G = 0.5). If the mixer is bypassed, the data passes unmodified (G = 1.0).
2. If the Root Raised Cosine Filter is enabled, a gain of G = 1.13 is introduced. If the RRC filters bypassed, the gain is unity.
3. If the integrate and Dump Filter is bypassed the Sample Pair summer has a gain of G = 1.0 and the 2
-7
-bit position is set to 1. If the integrate
and dump is enabled, the sample pair sum is scaled by one half (G = 0.5).
4. The negative sign on the MSBs indicates use of 2’s complement data format.
FIGURE 10. GAIN DISTRIBUTION AND INTERMEDIATE BIT WEIGHTINGS
(NOTE 4)
/
8
G
AGC
HSP50210
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSP50210JC-52 | Digital Costas Loop |
| HSP50216KI | Four-Channel Programmable Digital DownConverter |
| HSP50307SC | Burst QPSK Modulator |
| HSP50307EVAL1 | 2.0GHz to 2.7GHz DownConverter |
| HSP50415 | Wideband Programmable Modulator(寬帶可編程調(diào)制器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50210JI-52Z | 功能描述:上下轉(zhuǎn)換器 COSTAS DEMODULATOR 84 PLCC 52MHZ IND RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50214 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214AVC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50214AVI | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
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