參數(shù)資料
型號(hào)： HSP50210JI-52
廠商： INTERSIL CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Digital Costas Loop
中文描述： SPECIALTY TELECOM CIRCUIT, PQCC84
封裝： PLASTIC, MS-018AFA, LCC-84
文件頁(yè)數(shù)： 39/49頁(yè)
文件大?。?/td> 326K
代理商： HSP50210JI-52
3-291
TABLE 34. LOCK DETECTOR CONFIGURATION CONTROL REGISTER
DESTINATION ADDRESS = 20
BIT
POSITION
FUNCTION
DESCRIPTION
31-28
Reserved
Reserved. Set to 0 for proper operation.
27
False Lock
Accumulator Operation
This bit selects the input to the False Lock Accumulator.
0 = Frequency Error input enabled to accumulator.
1 = False Lock Bit enabled to accumulator.
26-20
Dwell Counter
Pre-load
The Dwell Counter holds off the Lock Accumulator integration for the number of integration cycles
programmed here. The length of the integration cycle is set in the bit positions 19-10. The 7-bit value
programmed here should be set to 1 less than the desired hold off time in integration cycles. The pre-
load is zeroed during Track Mode. Only used during stepped acquisition mode.
19-10
Integration Counter
Pre-Load
(Acquisition)
The Integration Counter controls the number Phase Error samples accumulated by the Lock
Accumulator. The 10-bit number loaded here is set to two less than the number of Phase Error samples
desired in the Integration Period. Total Range 2-1025. Bit 19 is the MSB.
9-0
Integration Counter
Pre-Load (Track)
Function is identical to Acquisition Integration Counter Pre-Load. See above.
TABLE 35. LOCK ACCUMULATOR PRE-LOADS CONTROL REGISTER
DESTINATION ADDRESS = 21
BIT
POSITION
FUNCTION
DESCRIPTION
31-16
Lock Accumulator Pre-
Load
(Acquisition)
The lock threshold is set by an accumulator pre-load which is backed off from the accumulator full scale
by the threshold amount. The Lock Accumulator is 18 bits and the accumulator bit weightings relative to
the magnitude of the Phase Error input and the pre-load is given below:
The accumulator roll over is at the 2
11
bit position.
15-0
Lock Accumulator Pre-
Load (Track)
Function is identical to Acquisition Lock Accumulation Pre-Load. See above.
TABLE 36. FALSE LOCK ACCUMULATOR PRE-LOAD CONTROL REGISTER
DESTINATION ADDRESS = 22
BIT
POSITION
FUNCTION
DESCRIPTION
31-16
False Lock
Accumulator
Pre-Load (Acquisition)
Depending on configuration, the input to the False Lock Accumulator is either the false lock indicator bit
or the magnitude of the frequency error detector output. Like the Lock Accumulator, the threshold is set
by an accumulator pre-load that is backed off from accumulator full scale. The False Lock Accumulator
can accumulate sums up to 18 bits, and the bit weightings of the false lock indicator bit and the frequency
error input relative to accumulator full scale are shown below.
The accumulator roll over is at the 2
11
bit position.
15-0
False Lock
Accumulator
Pre-Load (Track)
See above. The Lock Detector State Machine only uses the accumulator during the verify state during
which the Track parameters are used.
2
10
2
9
2
8
2
7
......2
0
.
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
BIT WEIGHTING OF
PHASE ERROR MAGNITUDE
BIT WEIGHTING OF ACCUMULATOR PRE-LOAD
BINARY POINT
2
10
2
9
2
8
2
7
......2
0
.
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
BIT WEIGHTING OF
FALSE LOCK INDICATOR BIT
BIT WEIGHTING OF ACCUMULATOR PRE-LOAD
BINARY POINT
BIT WEIGHTING OF
FREQUENCY ERROR MAGNITUDE
HSP50210
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