參數(shù)資料
型號: HSP50210JI-52
廠商: INTERSIL CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Digital Costas Loop
中文描述: SPECIALTY TELECOM CIRCUIT, PQCC84
封裝: PLASTIC, MS-018AFA, LCC-84
文件頁數(shù): 49/49頁
文件大?。?/td> 326K
代理商: HSP50210JI-52
3-301
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
Waveforms
FIGURE 26. TIMING RELATIVE TO WR
FIGURE 27. OUTPUT RISE AND FALL TIMES
FIGURE 28. TIMING RELATIVE TO CLK
FIGURE 29. OUTPUT ENABLE/DISABLE
FIGURE 30. TIMING RELATIVE TO READ
FIGURE 31. SERCLK TIMING
WR
C0-7, A0-2
t
WS
t
WH
t
WRH
t
WRL
t
RF
t
RF
0.8V
2.0V
CLK
IIN9-0, QIN9-0,
t
DS
t
DH
SYNC,
FZ_CT, FZ_ST
t
CL
t
CH
t
DO
t
CP
AOUT9-0, BOUT9-0,
COF, COFSYNC,
SOF, SOFSYNC,
HI/LO, SMBLCLK,
SLOCLK, LKINT, THRES
SERCLK, WR
t
SC
; t
WC
C7-0
t
CDO
1.7V
1.3V
1.5V
1.5V
t
OE
t
OD
OUTA9-0,
OUTB9-0
OEA,
OEB
t
RDO
C0-7
t
ROD
t
RL
RD
A2-0
t
ADO
ISER, QSER, SSYNC
t
DSS
t
SH
t
SL
t
DSH
SERCLK
HSP50210
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