參數(shù)資料
型號(hào)： HSP50210JI-52
廠商： INTERSIL CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Digital Costas Loop
中文描述： SPECIALTY TELECOM CIRCUIT, PQCC84
封裝： PLASTIC, MS-018AFA, LCC-84
文件頁(yè)數(shù)： 11/49頁(yè)
文件大?。?/td> 326K
代理商： HSP50210JI-52
3-263
The AGC Loop Filter integrates the scaled error signal to
provide a correction control term to the multipliers in the I and
Q path. The loop filter accumulator has internal upper and
lower limiters. The upper eight bits of the accumulator output
map to an exponent and mantissa format that is used to set
these upper and lower limits. The format, illustrated in Figure
8, is used for the AGC Upper Limit, AGC Lower Limit and the
Correction Control Term (AGC output). This format should not
be confused with the similar format used for the AGC Loop
Gain. The input to the AGC Loop Filter is included in Figure 8
to show the relative weighting of the input to output of the loop
filter. The loop filter input is represented as the eleven letter
“G”s. Lower case “e” and “m” detail the format for the AGC
Upper and Lower Limits. This change in type case should help
keep the AGC Limits and AGC Gain formats from being
confused. The AGC Upper and Lower Limits are set in the
AGC Loop Parameters Control Register, bits 0-15, (see Table
16). This 6-bit unsigned mantissa format provides for an AGC
output control range from 0.0000 to 0.9844, with a resolution
of 0.015625. The 2-bit exponent format provides an AGC
output control range from 1 to 8. The decimal values for each
of the 64 binary mantissa values is detailed in Table 4, while
Table 5 details the decimal value for the 4 exponent values.
The AGC Output is implemented in the multiplier according
to Equation 8.
where m and e are the binary values for mantissa and
exponent found in Tables 4 and 5.
NOTE:This format is identical to the format used to program the
AGC Upper and Lower Limits, but in this usage it is not a pro-
grammed value. It is a representation of the digital AGC output
number which is presented to the Gain Adjuster (multipliers) to
correct the gain of the I and Q data signals in the main data path.
These equations yield a composite (mantissa and
exponent) AGC output range of 0.0000 to 1.9844(2
3
) which
is a logarithmic range from 0 to 24dB. Figure 9 has graphed
the results of Equation 8 for both the linear and logarithmic
equations. Figure 9 also has a linear estimate of the
logarithmic equation. This linear approximation will be used
in calculating the AGC response time.
L
I
M
I
T
CARTESIAN TO POLAR
AGC ERROR DETECT
“0”
S
H
I
F
T
L
I
M
I
T
R
E
G
AGC LOOP FILTER
-
+
R
E
G
R
E
G
M
U
X
COMPARE
R
E
G
TAN
-1
( )
I
2
+Q
2
I
M
U
X
+
GAIN
ERROR
AGC
LIMIT
UPPER
AGC
LOWER
LIMIT
POWER
THRSHLD
AGC THRSHLD
AGC LOOP
GAIN
MANTISSA
(2
-7
TO 2
-14
)
ENABLE AGC
AGC LOOP
GAIN
EXPONENT
(0.000 TO 0.9375)
CART/POLAR INPUT SELECT
READ
REG
I&D FILTER
I&D FILTER
I
Q
MAGNITUDE
(0 - 1.1455)
PHASE
THRESH
GAIN
ADJUST
0.000 TO 1.07297(2
-7
)
1.0000 TO 15.8572 = G
AGC
(0 TO 24dB)
FIGURE 7. AGC LOOP BLOCK DIAGRAM
Indicates a microprocessor control signal.
AGC GAIN = (1.0 + M) x 2
E
G
AGC
1.0
0.8
G
12
=
dcloutlvl
agc thresh-----------
=
where dcloutlvl is the
magnitude output expressed
in dB from Full Scale (dBFS)
Out
AGC
linear
–
1.0
m
AGC
+
(
)
2
e
(
)
=
Out
AGC
dB
–
20 log
1.0
m
AGC
+
(
)
2
e
(
)
[
]
=
(EQ. 8A)
(EQ. 8B)
2
1
2
0
.2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
2
-8
2
-9
2
-10
2
-11
2
-12
2
-13
2
-14
2
-15
2
-16
2
-17
2
-18
e e .m m m m m m
G G
G
G
G
G
G
G
G
G
G
FIGURE 8. AGC OUTPUT AND AGC LIMITS BIT WEIGHTING
HSP50210
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