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參數(shù)資料
| 型號： | HSP50210JI-52 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Digital Costas Loop |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQCC84 |
| 封裝： | PLASTIC, MS-018AFA, LCC-84 |
| 文件頁數(shù)： | 32/49頁 |
| 文件大?。?/td> | 326K |
| 代理商： | HSP50210JI-52 |
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3-284
TABLE 15. POWER DETECT THRESHOLD CONTROL REGISTER
DESTINATION ADDRESS = 1
BIT
POSITION
FUNCTION
DESCRIPTION
31-8
Not Used
No programming required.
7-0
Power Threshold
The THRESH output is driven low when the magnitude output of the Cartesian to Polar Converter
exceeds the threshold programmed here. The threshold is represented as an 8-bit fractional unsigned
value with the following format:
2
0
. 2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.
Using this format, the possible range of threshold values is between 0 to 1.9961. Bit position 7 is the MSB.
TABLE 16. AGC LOOP PARAMETERS CONTROL REGISTER
DESTINATION ADDRESS = 2
BIT
POSITION
FUNCTION
DESCRIPTION
31
Enable AGC
0 = Gain error enabled to AGC Loop Filter.
1 = Gain error into AGC Loop Filter set to zero.
30-28
AGC Loop Gain
Exponent (E)
These bits set the loop gain exponent as given by:
AGC Loop Gain Exponent = 2
-(7 + EEE)
where EEE corresponds to the 3-bit binary value programmed here. Thus, a gain range from 2
-7
to 2
-14
may be achieved for EEE = 000 to 111 Binary. Bit position 30 is the MSB. See Table 3.
27-24
AGC Loop Gain
Mantissa (M)
The loop gain mantissa is represented as a 4-bit unsigned value with the following format:
AGC Loop Gain Mantissa = 0. 2
-1
2
-2
2
-3
2
-4
; 0.MMMM.
This format provides a mantissa range from 0.0 to 0.9375 for mantissa settings from 0000 to 1111 Binary.
Bit position 27 is the MSB. Mantissa resolution = 0.0625. See Table 2.
23-16
AGC Threshold
The AGC gain error is generated by subtracting the threshold value programmed here from the
magnitude value out of the Cartesian to Polar Converter. The binary format for the AGC Threshold is the
same as that for the Power Threshold given in Table 15.
15-8
AGC Upper Limit
The upper 8 bits of the AGC Accumulator set the AGC gain as given by Equation 8A. The value
programmed here sets upper limit for AGC gain by specifying a limit for the upper 8 bits of the AGC
accumulator. If the accumulated sum exceeds the upper limit, the accumulator is loaded with the limit.
These bits are packed as eemmmmmm where the e’s correspond to the exponent bits and the m’s
correspond to the mantissa bits of Equation 8 (see also Figure 8). Bit position 15 is the MSB. By setting the
AGC upper and lower limits to the same value, the AGC can be set to a fixed gain.
7-0
AGC Lower Limit
The value programmed here sets the lower limit for the upper 8 bits of the AGC accumulator in a manner
similar to that described for the upper limit. If the accumulated sum falls below the lower limit, the
accumulator is loaded with the limit. The format for these bits is as described for the upper limit. By setting
the AGC upper and lower limits to the same value, the AGC can be set to a fixed gain.
AGC THRESHOLD
VALUE
RESULTING OUTPUT
LEVEL (dBFS)
1.1453 (42h)
0
0.8108 (67h)
-3
0.5740 (49h)
-6
0.4064 (34h)
-9
0.2877 (24h)
-12
TABLE 17. CARRIER PHASE ERROR DETECTOR CONTROL REGISTER
DESTINATION ADDRESS = 3
BIT
POSITION
FUNCTION
DESCRIPTION
31-8
Not Used
No programming required.
7-6
Reserved
Reserved. Set to 0 for proper operation.
HSP50210
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50210JI-52Z | 功能描述:上下轉(zhuǎn)換器 COSTAS DEMODULATOR 84 PLCC 52MHZ IND RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50214 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214AVC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50214AVI | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
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