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參數(shù)資料
| 型號： | HSP50210JI-52 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Digital Costas Loop |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQCC84 |
| 封裝： | PLASTIC, MS-018AFA, LCC-84 |
| 文件頁數(shù)： | 38/49頁 |
| 文件大?。?/td> | 326K |
| 代理商： | HSP50210JI-52 |
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3-290
13-9
Symbol Tracking
Lead Gain Exponent
(Acquisition)
These bits set the lead gain exponent as given by:
Symbol Tracking Lead Gain Exponent = 2
-(32-E),
where E corresponds to the 5-bit binary value programmed here. Thus, a gain range from
2
-1
to 2
-32
relative to the MSB position of the NCO control word may be achieved for E = 11111 to 00000
Binary. Bit position 13 is the MSB.
8-5
Symbol Tracking Lag
Gain Mantissa
(Acquisition)
Format same as lead gain mantissa. Bit position 8 is the MSB.
4-0
Symbol Tracking Lag
Gain Exponent
(Acquisition)
Format same as lead gain exponent. Bit position 4 is the MSB.
TABLE 31. SYMBOL TRACKING LOOP FILTER GAIN (ACQ) CONTROL REGISTER (Continued)
DESTINATION ADDRESS = 17
BIT
POSITION
FUNCTION
DESCRIPTION
TABLE 32. SYMBOL TRACKING LOOP FILTER GAIN (TRK) CONTROL REGISTER
DESTINATION ADDRESS = 18
BIT
POSITION
FUNCTION
DESCRIPTION
31-24
Not Used
No programming required.
23-18
Reserved
Reserved. Set to 0 for proper operation.
17-14
Symbol Tracking Lead Gain Mantissa
(Track)
Format same as lead gain mantissa (see Table 31). Bit position 17 is the MSB.
13-9
Symbol Tracking Lead Gain Exponent
(Track)
Format same as lead gain exponent (see Table 31). Bit position 13 is the MSB.
8-5
Symbol Tracking Lag Gain Mantissa
(Track)
Format same as lead gain mantissa (see Table 31). Bit position 8 is the MSB.
4-0
Symbol Tracking Lag Gain Exponent
(Track)
Format same as lead gain exponent (see Table 31). Bit position 4 is the MSB.
TABLE 33. SYMBOL TRACKING LOOP FILTER LAG ACCUMULATOR INITIALIZATION CONTROL REGISTER
DESTINATION ADDRESS = 19
BIT
POSITION
FUNCTION
DESCRIPTION
N/A
Symbol Tracking Loop
Filter Lag Accumulator
Initialization
Writing to this address initializes the lag accumulator with the contents of the four Microprocessor
Interface Holding Registers at the start of the next loop filter computation cycle. The contents of the
holding registers should not be changed until after the start of a new compute cycle since the current
contents of the holding registers are loaded at the compute cycle start. At a slow rate, it could take 1 low
rate symbol time to change. The Microprocessor Interface should be used to read an internal status
register which signals when the lag accumulator load is complete (see Table 13 in the Microprocessor
Interface Section). The contents of the holding registers are loaded into the 32 MSBs of the lag
accumulator and the 8 LSBs are zeroed.
It is a good practice to load the LAG accumulators at the very end of a configuration load sequence.
HSP50210
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSP50210JC-52 | Digital Costas Loop |
| HSP50216KI | Four-Channel Programmable Digital DownConverter |
| HSP50307SC | Burst QPSK Modulator |
| HSP50307EVAL1 | 2.0GHz to 2.7GHz DownConverter |
| HSP50415 | Wideband Programmable Modulator(寬帶可編程調(diào)制器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50210JI-52Z | 功能描述:上下轉(zhuǎn)換器 COSTAS DEMODULATOR 84 PLCC 52MHZ IND RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50214 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214AVC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50214AVI | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
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