參數(shù)資料
型號: HSP50210JI-52
廠商: INTERSIL CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Digital Costas Loop
中文描述: SPECIALTY TELECOM CIRCUIT, PQCC84
封裝: PLASTIC, MS-018AFA, LCC-84
文件頁數(shù): 1/49頁
文件大?。?/td> 326K
代理商: HSP50210JI-52
3-253
HSP50210
Digital Costas Loop
The Digital Costas Loop (DCL) performs many of the
baseband processing tasks required for the demodulation of
BPSK, QPSK, 8-PSK, OQPSK, FSK, AM and FM
waveforms. These tasks include matched filtering, carrier
tracking, symbol synchronization, AGC, and soft decision
slicing. The DCL is designed for use with the HSP50110
Digital Quadrature Tuner to provide a two chip solution for
digital down conversion and demodulation.
The DCL processes the In-phase (I) and quadrature (Q)
components of a baseband signal which have been digitized
to 10 bits. As shown in the block diagram, the main signal
path consists of a complex multiplier, selectable matched
filters, gain multipliers, cartesian-to-polar converter, and soft
decision slicer. The complex multiplier mixes the I and Q
inputs with the output of a quadrature NCO. Following the
mix function, selectable matched filters are provided which
perform integrate and dump or root raised cosine filtering
(
α
~ 0.40). The matched filter output is routed to the slicer,
which generates 3-bit soft decisions, and to the cartesian-to-
polar converter, which generates the magnitude and phase
terms required by the AGC and Carrier Tracking Loops.
The PLL system solution is completed by the HSP50210
error detectors and second order Loop Filters that provide
carrier tracking and symbol synchronization signals. In
applications where the DCL is used with the HSP50110,
these control loops are closed through a serial interface
between the two parts. To maintain the demodulator
performance with varying signal power and SNR, an internal
AGC loop is provided to establish an optimal signal level at
the input to the slicer and to the cartesian-to-polar converter.
Features
Clock Rates Up to 52MHz
Selectable Matched Filtering with Root Raised Cosine or
Integrate and Dump Filter
Second Order Carrier and Symbol Tracking Loop
Filters
Automatic Gain Control (AGC)
Discriminator for FM/FSK Detection and Discriminator
Aided Acquisition
Swept Acquisition with Programmable Limits
Lock Detector
Data Quality and Signal Level Measurements
Cartesian to Polar Converter
8-Bit Microprocessor Control - Status Interface
Designed to work with the HSP50110 Digital
Quadrature Tuner
84 Lead PLCC
Applications
Satellite Receivers and Modems
BPSK, QPSK, 8-PSK, OQPSK, FSK, AM and FM
Demodulators
Digital Carrier Tracking
Related Products: HSP50110 Digital Quadrature Tuner,
D/A Converters HI5721, HI5731, HI5741
HSP50110/210EVAL Digital Demod Evaluation Board
Block Diagram
D
FILTER
CONTROL
INTERFACE
STATUS
BUS
10
13
CONTROL
OUT(9-0)
OUT(9-0)
TRACK
CONTROL
RRC
DUMP
INTEGRATE/
LOOP
FILTER
MAGNITUDE
PHASE
I
Q
10
8
8
CARRIER ACQ/TRK
LOOP FILTER
SYMBOL
TRACKING
LOOP FILTER
Q
I
LEVEL
DETECT
HI/LO
SLICER
CARTESIAN
TO
POLAR
FILTER
RRC
DUMP
INTEGRATE/
NCO
LEVEL
DETECT
COS
SIN
10
10
CARRIER
CONTROL/
3
3
8
8
LOCK
DETECT
SERCLK
OR CLK
Q SER OR
Q
IN
(9-0)
(COF)
(SOF)
A
B
SMBLCLK
THRESH
LKINT
OEA
OEB
STRACK
I SER OR
I
IN
(9-0)
CARRIER PHASE
ERROR DETECT
SYMBOL
PHASE
ERROR
DETECT
Data Sheet
January 1999
File Number
3652.4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
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