參數(shù)資料
型號(hào)： HSP50210JI-52
廠商： INTERSIL CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Digital Costas Loop
中文描述： SPECIALTY TELECOM CIRCUIT, PQCC84
封裝： PLASTIC, MS-018AFA, LCC-84
文件頁(yè)數(shù)： 45/49頁(yè)
文件大?。?/td> 326K
代理商： HSP50210JI-52
3-297
TABLE 44. INITIALIZE LOCK DETECTOR (
μ
P CONTROL MODE) CONTROL REGISTER
DESTINATION ADDRESS = 30
BIT
POSITION
FUNCTION
DESCRIPTION
N/A
Initialization of Lock
Detector Accumulators
Loading the address register with this destination address pre-loads all of the Lock Detector
Accumulators and resets the Integration Countersto restart the integration process.
Note: Awrite to this
address only initializes the Lock Detector when it is in microprocessor control mode (see
Acquisition/Tracking Control Register; Table 37).
TABLE 45. TEST CONFIGURATION CONTROL REGISTER
DESTINATION ADDRESS = 31
BIT
POSITION
FUNCTION
DESCRIPTION
31-16
Not Used
No programming required.
15-6
Reserved
Set to 0 for proper operation.
5
Initialize NCO
This bit is used to zero the feed back in the NCO’s phase accumulator. This is useful in setting the output
of the NCO to a known value.
0 = Enable normal NCO operation.
1 = Zero phase accumulator feedback for test.
4
Zero Symbol Tracking
Loop Filter
Accumulator
This bit is used to zero the lag accumulator in the Symbol Tracking Loop Filter.
0 = Enable normal loop filter operation.
1 = Zero Lag Accumulator.
3
ZeroCarrierLoopFilter
Accumulator
This bit is used to zero the lag accumulator in the Carrier Loop Filter.
0 = Enable normal loop filter operation.
1 = Zero Lag Accumulator.
2-0
Reserved
Set to 0 for proper operation.
TABLE 46. STATUS 6-0 SIGNAL DESCRIPTIONS
BIT
POSITION
FUNCTION
DESCRIPTION
6
Carrier Lock
0 = Lock Detector is not in locked state (Carrier Tracking Loop is not locked).
1 = Lock Detector has achieved the locked state (Carrier lock has been achieved).
5
Acquisition/Track
indicator
0 = Tracking Parameters currently being used by Tracking Loops.
1 = Acquisition Parameters currently being used by Tracking Loops.
4
Reserved
N/A.
3
Frequency Sweep
Direction
This bit indicates the direction of the frequency sweep selected by the Frequency Sweep input to the lag
path of the Carrier Tracking Loop Filter (Defined for upper sideband signals).
0 = Up (Sweep increasing in frequency).
1 = Down (Sweep decreasing in frequency).
2
High Power
This bit is one clock cycle long and indicates when the AGC is at its lower limit (see AGC Section and
Table 15).
0 = AGC above lower limit.
1 = AGC at lower limit.
1
Low Power
This bit is one clock cycle long and indicates when the AGC is at its upper limit (see AGC Section and
Table 15).
0 = AGC is at or below its upper limit.
1 = AGC is above its upper limit.
0
Data Ready Strobe
This bit pulses “High” for one CLK synchronous with a new signal output on OUTB6-0 (see Output
Selector Control Register: Table 45). For example if the lower 4 bits of the Output Selector Register are
set to 0010 (BINARY), This bit will pulse active on the same CLK that new FE7-1 data is output.
HSP50210
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