參數(shù)資料
型號： HSP50210JI-52
廠商： INTERSIL CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Digital Costas Loop
中文描述： SPECIALTY TELECOM CIRCUIT, PQCC84
封裝： PLASTIC, MS-018AFA, LCC-84
文件頁數(shù)： 24/49頁
文件大?。?/td> 326K
代理商： HSP50210JI-52
3-276
Verify.
Once phase lock is obtained, the frequency sweep is
disabled and the tracking parameters are enabled. Lock is
verified if the accumulated Phase Error is below the
threshold for a programmable number of Integration Periods.
False lock conditions are also monitored by comparing the
roll over of the False Lock Accumulator to that of the
Integration Counter. If the False Lock Accumulator rolls over
before the Integration Counter, a false lock condition exists.
False Lock.
Once a false lock has been determined, the
Frequency Sweep block is enabled to move the carrier
tracking beyond the false lock region. The Frequency Sweep
is performed for a programmable number of Integration
Periods before returning to the search state.
Lock.
When phase lock has been verified, the Lock status
output is asserted and the False Lock Detector is disabled.
The lock state is maintained as long as the Integration
Counter rolls over before the Phase Error Accumulator.
If the acquisition and tracking process is controlled externally,
the Phase Error Accumulator and False Lock Accumulators
are monitored by an external processor to determine when
lock has been achieved. In this mode the accumulator pre-
loads are typically set to zero and the accumulator output is
compared in the processor against a threshold equal to the
maximum Phase Error per sample times the number of
samples per Integration Period. The accumulators stop after
each Integration Period to hold their outputs for reading via
the Microprocessor Interface (see Read Enable Address Map;
Table 11). The accumulators are restarted by writing the
Initialize Lock Detector Control address (see Initialize Lock
Detector Control Register: Table 44). To simplify the processor
interface, the LKINT output is provided to interrupt the
processor when the accumulator integration period is
complete. The processor controls the use of the
acquisition/tracking parameters and lock status line by setting
the appropriate bits in the Acquisition/Tracking Configuration
Control Register (see Table 37). In addition, the frequency
sweep function is enabled via the Microprocessor Interface.
DWELL
COUNTER
INTEGRATION
COUNTER
LOCK DETECTOR STATE MACHINE
MUX
|X|
“0”
TRACK
INT
PERIOD
ACQ
INT
PERIOD
TRACK
PHASE
ERROR
PRELOAD
ACQ
PHASE
ERROR
PRELOAD
TRACK
PHASE
ERROR
FALSE
LOCK
PRELOAD
ACQ
FALSE
LOCK
PRELOAD
TRACK
FALSE LOCK/
FREQUENCY
ERROR
GAIN
ERROR
+
M
REG
MUX
|X|
+
M
|X|
+
M
“0”
ACQUIRE/
TRACK
OVERFLOW
OVERFLOW
MUX
MUX
DWELL
COUNT
ACQ
REG
REG
FIGURE 17. LOCK DETECTOR BLOCK DIAGRAM
TC
START
TC
SWEPT
HSP50210
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