參數(shù)資料
型號： HSP50210JI-52
廠商： INTERSIL CORP
元件分類： 通信及網(wǎng)絡
英文描述： Digital Costas Loop
中文描述： SPECIALTY TELECOM CIRCUIT, PQCC84
封裝： PLASTIC, MS-018AFA, LCC-84
文件頁數(shù)： 16/49頁
文件大?。?/td> 326K
代理商： HSP50210JI-52
3-268
Sampling Error Detector
The Sampling Error Detector is a decision based error
detector which determines sampling errors on both the I and
Q processing paths. The detector assumes that it is fed with
samples of the baseband waveform taken in the middle of
the symbol period (mid-symbol sample) and between
symbols (end-symbol sample) as shown in Figure 12. The
sampling error is a measure of how far the mid-symbol
sample is from the symbol transition mid-point. The
transition mid-point is half way between two symbol
decisions. The detector makes symbol decisions by
comparing the end-symbol samples against a selectable
threshold set (see Modulation Order Select bits 9-10 in Table
28). The error term is generated by subtracting the mid-
symbol sample from the transition mid-point. The sign of the
error term is negated for negatively sloped symbol
transitions. If no symbol transitions are detected the error
detector output is zeroed. Errors on both the I and Q
processing paths are summed and divided by two if Double
Rail error detection is selected (see Symbol Tracking
Configuration Control Register, bit 8: Table 28).
The sampling Error Detector provides an error accumulator
to compensate for the processing rate of the loop filter. The
error detector generates outputs at the symbol rate, but the
loop filter can only accept inputs every eight f
CLK
clocks.
Thus, if the symbol rate is faster than 1/8 CLK, the error
accumulator should be used to accumulate the error until the
loop filter is ready for a new input. If the error accumulator is
not used when the symbol rate exceeds 1/8 CLK, some error
outputs will be missed. For example, if f
CLK
= 40MHz, then
error accumulation is required for symbol rates greater than
5 MSPS (f
CLK
/8).
Note: The loop filter lead gain term
must be scaled accordingly if the accumulator is used.
Symbol Tracking Loop Filter
The Symbol Tracking Loop Filter is a second order lead/lag
filter. The sampling error is weighted by the lag gain and
accumulated to give the integral response (see Figure 11).
The Lag Accumulator output is summed with the sampling
error weighted by the Lead Gain. The result is a frequency
term which is output serially, via the SOF output, to the
NCO/VCO controlling the baseband sample rate (see Serial
Output Section). In basic configurations, the SOF output of
the HSP50210 is connected to the SOF input of the
HSP50110.
Two sets of registers are provided to store the loop gain
parameters associated with acquisition and tracking. The
appropriate loop gain parameters are selected manually via
the Microprocessor Interface or automatically via the Carrier
Lock Detector. The loop filter’s lead and lag gain terms are
represented as a mantissa and exponent. The mantissa is a
4-bit value which weights the loop filter input from 1.0 to
1.9375. The exponent defines a shift factor that provides
additional weighting from 2
-1
to 2
-32
. Together the loop gain
mantissa and exponent provide a gain range between 2
-32
and
~
1.0 as given by,
Lead/Lag Gain = (1.0+M*2
-4
)*2
-(32 -E)
(EQ. 10)
where M = a 4-bit binary number from 0 to 15, and E is a 5-bit
binary value ranging from 0 to 31. For example, if M = 0101
and E = 00110, the Gain = 1.3125*2
-26
. They are stored in the
Control Registers described in Table 31 and Table 32.
A limiter is provided on the lag accumulator output to keep the
baseband sample rate within a user defined range (see Table
29 and Table 30). If the lag accumulator exceeds either the
upper or lower limit, the accumulator is loaded with the limit.
For additional loop filter control, the loop filter output can be
frozen by asserting the FZ_ST pin which null the sampling
error term into the loop filter. The lag accumulator can be
initialized to a particular value and can be read via the
microprocessor interface as described in the Section
“Reading from the Microprocessor Interface”, and Table 33.
The symbol tracking loop filter bit weighting is identical to the
carrier tracking loop bit weighting, shown in Figures 9 and 10.
Soft Decision Slicer
The Soft Decision Slicer encodes the I/Q end-symbol
samples into 3-bit soft decisions. The input to the slicer is
assumed to be a bi-polar (2ary) baseband signal
representing encoded values of either ‘1’ or ‘0’. The most
significant bit of the 3-bit soft decision represents a hard
decision with respect to the mid-point between the expected
symbol values. The 2 LSBs represent a level of confidence
in the decision. They are determined by comparing the
magnitude of the slicer input to multiples (1x, 2x, and 3x) of a
programmable soft decision threshold (see Figure 13).
X
X
X
SAMPLING
ERROR
END-SYMBOL
SAMPLE
EXPECTED
SYMBOL
LEVELS
X
X
FIGURE 12. TRACKING ERROR ASSOCIATED WITH BASE-
BAND SAMPLING ON EITHER I OR Q RAIL
(BPSK/QPSK)
TRANSITION
MIDPOINT
MID-SYMBOL
SAMPLE
X
HSP50210
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相關代理商/技術參數(shù)
參數(shù)描述
HSP50210JI-52Z 功能描述:上下轉換器 COSTAS DEMODULATOR 84 PLCC 52MHZ IND RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128
HSP50214 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter
HSP50214A 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter
HSP50214AVC 制造商:Rochester Electronics LLC 功能描述:- Bulk
HSP50214AVI 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter
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