參數(shù)資料
型號(hào)： GS4911B
廠商： Gennum Corporation
英文描述： HD/SD/Graphics Clock and Timing Generator with GENLOCK
中文描述： 高清/標(biāo)清/圖形時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁(yè)數(shù)： 96/113頁(yè)
文件大?。?/td> 1017K
代理商： GS4911B
GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
96 of 113
Lines_Per_Field
52h
15-0
Contains the number of lines per field for the selected
output timing format.
This register is 15.1 encoded (i.e. bit 0 represents 0.5
when set HIGH and 0 when set LOW).
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing signals.
Otherwise, this register is read-only.
NOTE: When bit 0 of this register is programmed HIGH,
the device assumes an interlaced output. Otherwise it
assumes a progressive output. For example,
programming ‘262.5’d will result in an interlaced output
standard with 525 lines per frame. Programming ‘525’d
will result in a progressive output with 525 lines per
frame.
Reference:
Section 3.10 on page 74
R/W
–
Lines_Per_Vsync
53h
15-0
Contains the number of lines per active V Sync interval
for the selected output timing format.
This register is 15.1 encoded (i.e. bit 0 represents '0.5'
when set HIGH and '0' when set LOW).
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing signals.
Otherwise, this register is read-only.
Reference:
Section 3.10 on page 74
R/W
–
Vsync_To_First_Active_Line
54h
15-0
Contains the number of lines from the start of V Sync to
the start of active video for the selected output timing
format.
This register is 15.1 encoded (i.e. bit 0 represents '0.5'
when set HIGH and '0' when set LOW).
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing signals.
Otherwise, this register is read-only.
NOTE1: The value programmed in this register will be
increased by 1 by the device such that V Blanking signal
generated will be one line longer than programmed.
NOTE2: For the pre-programmed output video
standards 3, 5, and 7, the value contained in this
register is incorrectly reported as 17 lines, although the
actual timing produced is correct at 16 lines.
Reference:
Section 3.10 on page 74
R/W
–
Vsync_To_Last_Active_Line
55h
15-0
Contains the number of lines from the start of V Sync to
the end of active video for the selected output timing
format.
This register is 15.1 encoded (i.e. bit 0 represents '0.5'
when set HIGH and '0' when set LOW).
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing signals.
Otherwise, this register is read-only.
NOTE: The user cannot specify a custom vertical
blanking signal to end in the middle of a line. If this
occurs, the device will automatically adjust the timing of
the signal to fall at the beginning of the next line.
Reference:
Section 3.10 on page 74
R/W
–
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
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