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| 型號： | GS4911B |
| 廠商： | Gennum Corporation |
| 英文描述： | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| 中文描述： | 高清/標(biāo)清/圖形時鐘和定時發(fā)生器鎖相 |
| 文件頁數(shù)： | 101/113頁 |
| 文件大?。?/td> | 1017K |
| 代理商： | GS4911B |
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GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
101 of 113
V_Start_3
63h
15
Reserved. Set this bit to zero when writing to 63h.
–
–
63h
14-0
The value programmed in this register indicates the start
line number of the leading edge of the
user-programmed V Sync signal USER3_V. For
interlaced output standards, this value corresponds to
the odd field line number.
NOTE: The value programmed in this register must be
less than the value programmed in V_Stop_3.
Reference:
Section 3.8.3 on page 69
R/W
0
V_Stop_3
64h
15
Reserved. Set this bit to zero when writing to 64h.
–
–
64h
14-0
The value programmed in this register indicates the end
line number of the trailing edge of the user-programmed
V Sync signal USER3_V. For interlaced output
standards, this value corresponds to the odd field line
number.
NOTE: The value programmed in this register must not
exceed the maximum number of lines per field of the
outgoing standard.
Reference:
Section 3.8.3 on page 69
R/W
0
Operator_Polarity_3
65h
15-4
Reserved. Set these bits to zero when writing to 65h.
–
–
65h
3
Polarity_3 - Use this bit to invert the polarity of the final
USER3 signal.
By default, the polarity of the user programmed signals
is active LOW. The polarity may be switched to active
HIGH by setting this bit LOW.
Reference:
Section 3.8.3 on page 69
R/W
1
65h
2
AND_3 - logical operator: USER3_H AND USER3_V
Set this bit HIGH to output a signal that is only active
when both USER3_H and USER3_V are active.
When this bit is HIGH, bit 1 and bit 0 of this register will
be ignored.
Reference:
Section 3.8.3 on page 69
R/W
0
65h
1
OR_3 - logical operator: USER3_H OR USER3_V
Set this bit HIGH to output a signal that is active
whenever USER3_H or USER3_V are active.
When this bit is HIGH bit 0 of this register will be
ignored.
Reference:
Section 3.8.3 on page 69
R/W
0
65h
0
XOR_3 - logical operator: USER3_H XOR USER3_V
Set this bit HIGH to output a signal with the following
attributes: Signal becomes active when either
USER3_H or USER3_V is active. Signal is inactive
when USER3_H and USER3_V are both active or both
inactive.
Reference:
Section 3.8.3 on page 69
R/W
0
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS4911BCNE3 | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4915 | CONN,S/R,8 POS,254C-08-1, CLOSED END STRAIN RELIEF COVER |
| GS6332 | 3 Pin, Low-Power, P Reset Circuits |
| GS6332UR15D1 | 3 Pin, Low-Power, P Reset Circuits |
| GS6333UR19D1 | FC/ACP F.O. SINGLE MODE IN-LINE ATTENUATOR 10DB |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS4911B_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4915 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:ClockCleaner |
| GS4915_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:ClockCleaner |
| GS4915-CNE3 | 制造商:Semtech Corporation 功能描述:QFN-40 pin (490/tray) |
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