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| 型號： | GS4911B |
| 廠商： | Gennum Corporation |
| 英文描述： | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| 中文描述： | 高清/標清/圖形時鐘和定時發(fā)生器鎖相 |
| 文件頁數(shù)： | 26/113頁 |
| 文件大?。?/td> | 1017K |
| 代理商： | GS4911B |
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GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
26 of 113
V Sync
The V Sync timing signal has a leading edge at the start of the vertical sync
pulse. Its length is determined by the selected video standard (see
Table 1-2
),
or according to custom timing parameters programmed in the host interface
(see
Section 3.10 on page 74
).
The leading edge of V Sync is nominally simultaneous with the leading edge of
the first broad pulse.
When in Genlock mode, the output V Sync signal will be phase locked to the
reference VSYNC input. This timing may be offset using the Genlock Offset
registers beginning at address 1Bh of the host interface (see
Section 3.2.1.1 on
page 37
).
By default, after system reset, the polarity of the V Sync signal output will be
active LOW. The polarity may be selected as active HIGH by programming the
Polarity register at address 56h of the host interface (see
Section 3.12.3 on
page 79
).
TIMING_OUT_3
V Blanking
The V Blanking signal is used to indicate the portion of the video field/frame not
containing active video lines.
The V Blanking signal will be LOW (default polarity) for the portion of the
field/frame containing valid video data, and will be HIGH throughout the vertical
blanking period.
The width of this signal will be determined by the selected video standard (see
Table 1-2
), or according to custom timing parameters programmed in the host
interface (see
Section 3.10 on page 74
).
When in Genlock mode, the output V Blanking signal will be phase locked to the
reference VSYNC input. This timing may be offset using the Genlock Offset
registers beginning at address 1Bh of the host interface (see
Section 3.2.1.1 on
page 37
).
The default polarity of this signal may be inverted by programming the Polarity
register at address 56h of the host interface (see
Section 3.12.3 on page 79
).
NOTE: When VID_STD = 4, 6, or 8, the Vblank output pulse width is 2 lines too
long for field 1 and 1 line too short for field 2 when compared to the digital timing
defined in ITU-R BT.656 and ITU-R BT.799.
TIMING_OUT_4
F Sync
The F Sync signal is used to indicate field 1 and field 2 for interlaced video
formats.
The F Sync signal will be HIGH (default polarity) for the entire period of field 1. It
will be LOW for all lines in field 2 and for all lines in progressive scan systems.
The width and timing of this signal will be determined by the V Sync parameters
of the selected video standard (see
Table 1-2
), or according to custom V Sync
timing parameters programmed in the host interface (see
Section 3.10 on
page 74
). The F Sync signal always changes state on the leading edge of V
Sync.
When in Genlock mode, the output F Sync signal will be phase locked to the
reference FSYNC input. This timing may be offset using the Genlock Offset
registers beginning at address 1Bh of the host interface (see
Section 3.2.1.1 on
page 37
).
The default polarity of this signal may be inverted by programming the Polarity
register at address 56h of the host interface (see
Section 3.12.3 on page 79
).
TIMING_OUT_5
Table 1-3: Output Timing Signals (Continued)
Signal Name
Description
Default Output Pin
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| GS4911B_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4915 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:ClockCleaner |
| GS4915_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:ClockCleaner |
| GS4915-CNE3 | 制造商:Semtech Corporation 功能描述:QFN-40 pin (490/tray) |
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