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參數(shù)資料
| 型號： | GS4911B |
| 廠商： | Gennum Corporation |
| 英文描述： | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| 中文描述： | 高清/標(biāo)清/圖形時鐘和定時發(fā)生器鎖相 |
| 文件頁數(shù)： | 75/113頁 |
| 文件大小： | 1017K |
| 代理商： | GS4911B |
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GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
75 of 113
3.11 Extended Audio Mode for HD Demux using the Gennum Audio
Core
The GS4911B/GS4910B has been designed to interface with Gennum's FPGA
Audio Core in order to provide a 24.576MHz clock (512 * 48kHz) locked to the
audio clock contained in the embedded audio data packets of an HD-SDI stream.
It is the responsibility of the user to divide this clock by 4 to obtain the 6.144MHz
required by the core.
In HD Demux mode, the FPGA Audio Core will extract an audio clock from the
embedded audio data packets and present a 24kHz clock to the
GS4911B/GS4910B via the aclkdiv2a (for Group A) and aclkdiv2b (for Group B)
outputs. The embedded clock must be 48kHz.
The 24kHz reference signals for each audio group must be applied to the HSYNC
input pin of a GS4911B/GS4910B, while a divided version of this signal must be
applied to the VSYNC input pin. The divided signal must meet the requirements for
VSYNC validity given in
Section 3.5.2 on page 45
. It is recommended that the
VSYNC signal be generated by dividing the 24kHz reference applied to HSYNC by
512 to give 46.875Hz.
To enable the extended audio mode, the user must do the following:
1. Set VID_STD[5:0] = 04h.
2. Set the F_Lock_Mask and V_Lock_Mask bits [4:3] of register address 16h to
1.
3. Set the Ext_Audio_Mode register address 81h to 20C1h.
4. Toggle the Update_Custom_V_Clock bit [6] of register address 16h.
In this mode, the GS4911B/GS4910B will produce a 24.576MHz clock on its PCLK
output pins that is locked to the 24kHz extracted audio clock reference applied to
HSYNC. It will not lock to any other reference frequency. The user may then divide
this frequency by 4 using the programmable dividers in the GS4911B/GS4910B.
Figure 3-13: Audio Clock Block Diagram for HD Demux Operation
FPGA
aout1_2
aout3_4
aout5_6
aout7_8
Serial
Video
Input
HD AUDIO
DEMUX CORE
PCLK
GS49xxB
Video Data
wclka
GS1559
Deserializer
aclk64a
wclkb
PCLK1
aclk128b
aclk64b
vin[19:0]
pclk
aclkdiv2b
aclkdiv2a
PCLK1
GS49xxB
aclk128a
/512
/512
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| GS4911B_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4915 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:ClockCleaner |
| GS4915_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:ClockCleaner |
| GS4915-CNE3 | 制造商:Semtech Corporation 功能描述:QFN-40 pin (490/tray) |
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