參數(shù)資料
型號(hào)： GS4911B
廠商： Gennum Corporation
英文描述： HD/SD/Graphics Clock and Timing Generator with GENLOCK
中文描述： 高清/標(biāo)清/圖形時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁(yè)數(shù)： 61/113頁(yè)
文件大小： 1017K
代理商： GS4911B
GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
61 of 113
GS4911B/GS4910B to crash lock whenever it sees a disturbance of the input H
signal.
NOTE: Any action that causes an abrupt phase change of the H input to the
GS4911B/GS4910B such that REF_LOST is not triggered will cause the device to
respond in the manner described above.
In addition to the slow drifting behaviour outlined above, there may also be a
random phase difference between the input VSYNC and output V Sync signals
occurring each time a switch in the SDI stream causes an abrupt phase change of
the H input to the GS4911B/GS4910B. This will only occur when attempting to lock
the "
f/1.001
" HD output standards to the 525-line SD input references standards,
or vice versa. For cases where the user must manually video genlock the device,
the problem will occur whenever the value programmed for H_Reference_Divide
(registers 2B-2Ah) is greater than 1. All line-based timing outputs are affected.
The only way to ensure a constant phase difference between the input VSYNC
signal and the line-based timing outputs is to reset the line-based counters after
such a switch occurs. This is acheived by toggling bit 15 of register address 83h in
the host interface. The device will then delay all line-based output timing signals by
Δ
Vsync lines relative to the input VSYNC reference, as described in NOTE 3 of
Section 3.2.1.1 on page 37
.
3.7 Clock Synthesis
The clock synthesis circuit generates the video/graphics clocks based on the
VID_STD[5:0] pins and host register settings. In the GS4911B, the clock synthesis
circuit also generates the audio clock signals based on the ASR_SEL[2:0] pins and
host register settings.
The generated video and audio clocks may be further divided and are presented to
the application layer via pins PCLK1-PCLK3 and ACLK1-ACLK3 respectively.
3.7.1 Video Clock Synthesis
The programmable video clock generator is referenced to an internal crystal
oscillator and is responsible for generating the PCLK output signals.
The crystal oscillator requires an external 27MHz crystal connected to pins X1 and
X2, or can be driven at LVTTL levels from an external 27MHz source connected to
X1. These two configurations are shown in
Figure 1-1
.
A range of 8 different video sample clock rates and 13 different graphic display
clock rates may be selected using the VID_STD[5:0] pins of the device.
Section 1.4
on page 20
lists the video and graphic formats available using the VID_STD[5:0]
pins. Once the device is powered up and an initial output format is selected using
VID_STD[5:0], the video clock rate may also be modified via the host interface (see
Section 3.9 on page 72
).
If desired, the external VID_STD[5:0] pins may be ignored by setting bit 1 of the
Video_Control register, and the video standard may instead be selected via the
VID_STD[5:0] register of the host interface (see
Section 3.12.3 on page 79
).
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