參數(shù)資料
型號(hào)： GS4911B
廠(chǎng)商： Gennum Corporation
英文描述： HD/SD/Graphics Clock and Timing Generator with GENLOCK
中文描述： 高清/標(biāo)清/圖形時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁(yè)數(shù)： 89/113頁(yè)
文件大小： 1017K
代理商： GS4911B
GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
89 of 113
PCLK2_Phase/Divide
2Dh
15-7
Reserved. Set these bits to zero when writing to 2Dh.
–
–
2Dh
6
Current_P2 - selects the current drive capability of the
PCLK2 pin. Set this bit HIGH for high current drive.
Otherwise, the current drive will be low.
NOTE: The current drive should be set high if PCLK2 is
greater than 100MHz.
Reference:
Section 3.7.1 on page 61
R/W
0
2Dh
5-2
PCLK2_Phase - adjusts the output phase of the PCLK2
clock with respect to the timing output pins. Phase is
delayed in 700ps (nominal) increments as shown in
Table 3-6
.
Reference:
Section 3.7.1 on page 61
R/W
0
2Dh
1
Divide_By_4 - set this bit HIGH to divide the output
PCLK2 by four.
NOTE: Setting this bit and bit 0 simultaneously HIGH
will hold the PCLK2 pin LOW.
Reference:
Section 3.7.1 on page 61
R/W
0
2Dh
0
Divide_By_2 - set this bit HIGH to divide the output
PCLK2 by two.
NOTE: Setting this bit and bit 1 simultaneously HIGH
will hold the PCLK2 pin LOW.
Reference:
Section 3.7.1 on page 61
R/W
0
PCLK3_Phase/Divide
2Eh
15-6
Reserved. Set these bits to zero when writing to 2Eh.
–
–
2Eh
5-2
PCLK3_Phase - adjusts the output phase of the
PCLK3/PCLK3 clock with respect to the timing output
pins. Phase is delayed in 700ps (nominal) increments
as shown in
Table 3-6
.
Reference:
Section 3.7.1 on page 61
R/W
0
2Eh
1
Divide_By_4 - set this bit HIGH to divide the output
PCLK3/PCLK3 by four.
Setting this bit and bit 0 simultaneously HIGH will give
the full rate video clock on the PCLK3 / PCLK3 pins.
Reference:
Section 3.7.1 on page 61
R/W
0
2Eh
0
Divide_By_2 - set this bit HIGH to divide the output
PCLK3/PCLK3 by two.
Setting this bit and bit 1 simultaneously HIGH will give
the full rate video clock on the PCLK3 / PCLK3 pins.
Reference:
Section 3.7.1 on page 61
R/W
0
PCLK3_Tristate
2Fh
15-2
Reserved. Set these bits to zero when writing to 2Fh.
–
–
2Fh
1-0
Set these bits to 11b to tristate the PCLK3 / PCLK3 pins.
Reference:
Section 3.7.1 on page 61
R/W
00b
RSVD
2Fh - 30h
–
Reserved.
–
–
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
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