參數資料
型號： GS4911B
廠商： Gennum Corporation
英文描述： HD/SD/Graphics Clock and Timing Generator with GENLOCK
中文描述： 高清/標清/圖形時鐘和定時發(fā)生器鎖相
文件頁數： 45/113頁
文件大小： 1017K
代理商： GS4911B
GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
45 of 113
3.4.3 Automatic Polarity Recognition
To accommodate any standards that employ the polarity of the H and V sync
signals to indicate the format of the display, the GS4911B/GS4910B will recognize
H and V sync polarity and automatically synchronize to the leading edge.
The polarities of the HSYNC and VSYNC signals are reported in bits 3 and 4 of the
Video_Status register. Additionally, bit 2 of this register reports the detection of
either analog or digital input timing. See
Section 3.12.3 on page 79
for detailed
register descriptions.
3.5 Reference Format Detector
The reference format detector checks the validity and analyzes the format of the
input reference signal. It is designed to accurately differentiate between 59.94 and
60Hz frame rates.
3.5.1 Horizontal and Vertical Timing Characteristic Measurements
When a reference signal is applied to the designated input pins, the
GS4911B/GS4910B will analyse the signal and report the following in registers
0Ah to 0Eh of the host interface:
the number of 27MHz clock pulses between leading edges of the H input
reference signal (H_Period register)
the number of 27MHz clock pulses in 16 horizontal periods (H_16_Period
register)
the number of H reference pulses between leading edges of the V input
reference signal (V_Lines register)
the number of H reference pulses in two vertical periods (V_2_Lines register)
the number of H reference pulses in one F period (F_Lines register)
These parameters may be read via the host interface and are used by the device
to determine reference signal validity.
3.5.2 Input Reference Validity
Before the device attempts to operate in Genlock mode, the input signals applied
to HSYNC and VSYNC must be valid and must conform to one of the 36
recognized video standards or 16 recognized graphics standards described in
Section 1.4 on page 20
. Alternatively, if VID_STD[5:0] = 62, the device may be
manually programmed to genlock to a reference that is neither valid nor recognized
(see
Section 3.10.1 on page 74
).
For an input reference signal to be considered valid, the periodicity of HSYNC must
be between 9us and 70us, and the periodicity of VSYNC must be between 8ms and
50ms. The FSYNC signal is not essential for validity. For output video standards
other than VID_STD[5:0] = 62, the REF_LOST pin will be set LOW once the input
reference signal is considered valid.
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