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參數(shù)資料
| 型號： | GS4911B |
| 廠商： | Gennum Corporation |
| 英文描述： | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| 中文描述： | 高清/標清/圖形時鐘和定時發(fā)生器鎖相 |
| 文件頁數(shù)： | 69/113頁 |
| 文件大?。?/td> | 1017K |
| 代理商： | GS4911B |
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GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
69 of 113
Figure 3-10: AFS Output Timing
The phasing of the divide by n counter can be controlled by the 10FID input or via
designated registers in the host interface.
By default, the 10FID input pin controls the AFS phase (in addition to controlling
the 10FID phase); however, this feature may be disabled by setting bit 0 of the
Audio_Control register (see
Section 3.12.3 on page 79
). In addition, the AFS signal
may be reset via register 1Ah.
3.8.3 USER_1~4
As described in
Table 1-3
, the GS4911B/GS4910B offers 4 user programmable
output signals which are available independent of the selected output video format.
Each user signal is individually programmable and the polarity, position, and width
of each output may be defined with respect to the digital output timingof the device.
Each output signal may be programmed in both the horizontal and vertical
dimensions relative to the leading edges of H blanking and V blanking. If desired,
the pulses produced may then be combined with a logical AND, OR, or XOR
function to produce a composite signal (for example, a horizontal back porch pulse
during active lines only, or the active part of lines 15 through 20 for vertical
information retrieval).
By default, the AND, OR, and XOR functions are disabled. Therefore, when a
USER signal is selected using the Output_Select registers of the host interface, the
signal will go LOW (default polarity) at the H_Start pixel and return HIGH after the
H_Stop pixel. Setting the AND bit HIGH, for example, will cause the USER signal
to be active only when USER_H is active and USER_V is active (i.e. the pixel is
between both H_Start and H_Stop and V_Start and V_Stop). See
Figure 3-11
.
NOTE: The effective horizontal range of the four user-defined timing signals is
[H_Start + 1, H_Stop], except when H_Start = 1, in which case the range is
[H_Start, H_Stop]. This prevents the user from specifying an output USER signal
that begins on pixel 2 of a line.
AFS_OUT
Horizontal Sync Output
Total Line
Line 1 every n frames where:
n = 1 @ 25fps: fs = 32kHz
n = 1 @ 25fps, 30fps & 60fps: fs = 44.1kHz
n = 1 @ 25fps, 30fps & 60fps; fs = 48kHz
n = 2 @ 24fps; fs = 44.1kHz, 48kHz
n = 3 @ 24fps, 30fps & 60fps: fs = 32kHz
n = 5 @ 29.97fps & 59.94fps; fs = 48kHz
n = 15 @ 29.97fps & 59.94fps; fs = 32kHz
n = 100 @ 29.97fps; fs = 44.1kHz
n = 200 @ 59.94fps; fs = 44.1kHz
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相關(guān)代理商/技術(shù)參數(shù) |
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| GS4911B_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4915 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:ClockCleaner |
| GS4915_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:ClockCleaner |
| GS4915-CNE3 | 制造商:Semtech Corporation 功能描述:QFN-40 pin (490/tray) |
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