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參數(shù)資料
| 型號： | GS4911B |
| 廠商： | Gennum Corporation |
| 英文描述： | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| 中文描述： | 高清/標(biāo)清/圖形時鐘和定時發(fā)生器鎖相 |
| 文件頁數(shù)： | 95/113頁 |
| 文件大小： | 1017K |
| 代理商： | GS4911B |
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GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
95 of 113
RSVD
4Bh
–
Reserved.
–
–
Video_Control
4Ch
15-5
Reserved. Set these bits to zero when writing to 4Ch.
–
–
4Ch
4
10FID_F_pulse - set this bit HIGH to stretch the 10FID
pulse duration from 1 line to 1 field.
Reference:
Section 3.8.1 on page 67
R/W
0
4Ch
3-2
Reserved. Set these bits to zero when writing to 4Ch.
–
–
4Ch
1
Host_VID_STD - set this bit HIGH to select the output
video standard using register 4Dh instead of the
external VID_STD[5:0] pins.
The external VID_STD[5:0] pins will be ignored, but
should not be left floating.
Reference:
Section 1.4 on page 20
R/W
0
4Ch
0
Reserved. Set this bit to zero when writing to 4Ch.
–
–
VID_STD[5:0]
4Dh
15-6
Reserved. Set these bits to zero when writing to 4Dh.
–
–
4Dh
5-0
Replaces the external VID_STD[5:0] pins when
VID_From_Host (bit 1 of address 4Ch) is HIGH.
Reference:
Section 1.4 on page 20
R/W
00h
Clocks_Per_Line
4Eh
15-0
Contains the number of output video clock cycles per
line for the selected output timing format.
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing signals.
Otherwise, this register is read-only.
Reference:
Section 3.10 on page 74
R/W
–
Clocks_Per_Hsync
4Fh
15-0
Contains the number of output video clock cycles in the
active H Sync interval for the selected output timing
format.
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing signals.
Otherwise, this register is read-only.
Reference:
Section 3.10 on page 74
R/W
–
Hsync_To_SAV
50h
15-0
Contains the number of output video clock cycles from
the start of H Sync to the start of active video for the
selected output timing format.
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing signals.
Otherwise, this register is read-only.
Reference:
Section 3.10 on page 74
R/W
–
Hsync_To_EAV
51h
15-0
Contains the number of output video clock cycles from
the start of H Sync to the end of active video for the
selected output timing format.
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing signals.
Otherwise, this register is read-only.
Reference:
Section 3.10 on page 74
R/W
–
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
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| GS4911BCNE3 | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS4911B_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4915 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:ClockCleaner |
| GS4915_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:ClockCleaner |
| GS4915-CNE3 | 制造商:Semtech Corporation 功能描述:QFN-40 pin (490/tray) |
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