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參數(shù)資料
| 型號： | CL-PS7111 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | Low-Power System-on-a-Chip |
| 中文描述： | 低功耗系統(tǒng)級晶片 |
| 文件頁數(shù)： | 89/105頁 |
| 文件大?。?/td> | 1207K |
| 代理商： | CL-PS7111 |
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PRELIMINARY DATA BOOK v2.0
September 1997
88
ELECTRICAL SPECIFICATIONS
CL-PS7111
Low-Power System-on-a-Chip
6.6.1
Oscillator and PLL Bypass Mode
This mode is selected by NTEST0 = 1, NTEST1 = 0.
In this mode all the internal oscillators and PLL are disabled and the appropriate crystal oscillator pins
become the direct external oscillator inputs bypassing the oscillator and PLL. MOSCIN must be driven by
a 36.864-MHz clock source and RTCOUT by a 32.768-kHz source. In addition the OSCEN (oscillator
enable) signal is multiplexed out on the PD[0] pin and can be used to control the external oscillator. The
functionality of the CL-PS7111 is not affected in any other way during this test mode.
6.6.2
Functional (EPB) Test Mode
This mode is selected by NTEST0 = 0, NTEST1 = 1, Latched NURESET = 1.
The functional EPB (embedded peripheral bus) Test mode is used for running test patterns, both through
the EPB external test interface and other patterns, and is used to test individual peripherals and the
ARM710a microprocessor. The PLL is automatically bypassed in this mode. In this mode various pins are
used as control inputs or outputs, as listed in
Table 6-3
. Note that in EPB test mode, the chip only wakes
up from the standby state using the external wake-up input. In this mode, the OR function of the Port A
inputs which can be used to wake-up the chip is not available.
6.6.3
Oscillator and PLL Test Mode
This mode is selected by NTEST0 = 0, NTEST1 = 1, Latched NURESET = 0.
This test mode enables the main oscillator and output various buffered clock and test signals derived from
the main oscillator, PLL, and 32-kHz oscillator. All internal logic in the CL-PS7111 is static and isolated
from the oscillators with the exception of the 6-bit ripple counter used to generate 576-kHz and the real-
time clock divide chain. Port A is used to drive the inputs of the PLL directly and the various clock and PLL
outputs are monitored on the COL pins.
Table 6-4
defines the CL-PS7111 signal pins used in this test
mode. This mode is only intended to allow tests of the oscillators and PLL.
Table 6-3.
EPB Test Mode Signal Assignment
Signal
I/O
Pin
Function
TSTA
I
PA0
EPB test control A
TSTB
I
PA1
EPB test control B
TSTSTART
I
PA2
Fast start speed up RTC divider chain
TSTDIRCLK
I
PA3
Insertion point for EPB test clock
TSTVCOUNT
I
PA4
Video Address counter increments faster
TACK
O
word
EPB test acknowledge output
Table 6-4.
Oscillator and PLL Test Mode Signals
Signal
I/O
Pin
Function
TSEL
a
I
PA5
PLL test select
XTALON
a
I
PA4
Enable to oscillator circuit
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相關(guān)代理商/技術(shù)參數(shù) |
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| CL-PS7500FE | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:System-on-a Chip for Internet Appliance |
| CLPT-12SP-06 | 制造商:Tri-Star Electronics International 功能描述:CONNECTOR - Bulk |
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