參數(shù)資料
型號: CL-PS7111
廠商: Cirrus Logic, Inc.
英文描述: Low-Power System-on-a-Chip
中文描述: 低功耗系統(tǒng)級晶片
文件頁數(shù): 79/105頁
文件大?。?/td> 1207K
代理商: CL-PS7111
PRELIMINARY DATA BOOK v2.0
September 1997
78
ELECTRICAL SPECIFICATIONS
CL-PS7111
Low-Power System-on-a-Chip
Figure 6-2. Expansion and ROM Sequential Read Timing
NOTES:
1)
t
EXBST
= 35 ns at 18.432 MHz and 55 ns maximum at 13.0 MHz for zero wait state page mode access. This
time can be extended by integer multiples of the clock period by either driving EXPRDY low and/or by pro-
gramming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before the data trans-
fer, if low at this point the transfer is delayed by one clock period where EXPRDY is sampled again. EXPCLK
need not be referenced when driving EXPRDY but is shown for clarity.
2)
Consecutive reads with sequential access enabled are identical except that the sequential access wait state
field is used to determine the number of wait states, and no idle cycles are inserted between successive non
sequential ROM/expansion cycles. This improves performance, so the SQAEN should always be set where
possible.
EXPCLK
t
5
t
1
t
6
t
4
t
3
NMOE
A[27:4]
D[31:0]
WORD
NCS[5:0]
EXPRDY
t
3
t
4
Sequential page mode read cycles with minimum wait states
A[3:0]
t
EXBST
t
EXBST
4
8
0
t
3
t
4
DATA IN
DATA IN
DATA IN
BUS HELD
t
EXRD
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