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參數(shù)資料
| 型號： | CL-PS7111 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | Low-Power System-on-a-Chip |
| 中文描述： | 低功耗系統(tǒng)級晶片 |
| 文件頁數(shù)： | 4/105頁 |
| 文件大?。?/td> | 1207K |
| 代理商： | CL-PS7111 |
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PRELIMINARY DATA BOOK v2.0
September 1997
4
OVERVIEW
CL-PS7111
Low-Power System-on-a-Chip
Table of Contents
1.
2.
CONVENTIONS...................................................................................................................... 6
PIN INFORMATION................................................................................................................ 8
2.1
Pin Diagram ...........................................................................................................................................8
2.2
Pin Descriptions.....................................................................................................................................9
2.2.1
External Signal Functions .........................................................................................................9
2.2.2
Numeric Pin Listing.................................................................................................................12
FUNCTIONAL DESCRIPTION............................................................................................. 16
3.1
Main Functional Blocks........................................................................................................................18
3.2
System Maximization...........................................................................................................................20
3.3
Endian Functionality.............................................................................................................................21
3.4
CPU Core.............................................................................................................................................22
3.5
Counters...............................................................................................................................................22
3.5.1
Free-Running Mode ................................................................................................................23
3.5.2
Prescale Mode........................................................................................................................23
3.6
Realtime Clock.....................................................................................................................................23
3.7
State Control........................................................................................................................................23
3.8
Expansion and ROM Interface.............................................................................................................25
3.8.1
CL-PS7111 Boot ROM............................................................................................................26
3.8.2
CL-PS6700 PCMCIA controller interface................................................................................27
3.9
DRAM Controller..................................................................................................................................30
3.10 LCD Controller .....................................................................................................................................33
3.11 Two Internal UARTs and SIR Encoder.................................................................................................34
3.12 Clocks ..................................................................................................................................................35
3.13 Interrupt Controller...............................................................................................................................37
3.13.1 Interrupt Latencies in Different States.....................................................................................38
3.14 Resets..................................................................................................................................................39
3.15 Two DC-to-DC Converters ...................................................................................................................40
3.16 Serial Interface.....................................................................................................................................40
3.16.1 Codec Interface.......................................................................................................................41
3.16.2 ADC Interface — Master-Mode Only SSI (Synchronous Serial Interface)..............................41
MEMORY MAP ..................................................................................................................... 43
REGISTER DESCRIPTIONS................................................................................................ 44
5.1
Port A Data Register — PADR.............................................................................................................47
5.2
Port B Data Register — PBDR.............................................................................................................47
5.3
Port D Data Register — PDDR............................................................................................................47
5.4
Port A Data Direction Register — PADDR...........................................................................................47
5.5
Port B Data Direction Register — PBDDR...........................................................................................47
5.6
Port D Data Direction Register — PDDDR ..........................................................................................47
5.7
Port E Data Register — PEDR.............................................................................................................47
5.8
Port E Data Direction Register — PEDDR...........................................................................................47
5.8.1
System Control Register 1 — SYSCON1 ...............................................................................48
5.9
System Status Flags Register 1 — SYSFLG1.....................................................................................50
5.10 Memory Configuration Register 1 — MEMCFG1.................................................................................53
5.10.1 Memory Configuration Register 2 — MEMCFG2....................................................................54
5.11 DRAM Refresh Period Register — DRFPR .........................................................................................57
5.12 Interrupt Status Register 1 — INTSR1.................................................................................................58
5.13 Interrupt Mask Register 1 — INTMR1..................................................................................................60
3.
4.
5.
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