參數(shù)資料
型號(hào)： CL-PS7111
廠(chǎng)商： Cirrus Logic, Inc.
英文描述： Low-Power System-on-a-Chip
中文描述： 低功耗系統(tǒng)級(jí)晶片
文件頁(yè)數(shù)： 64/105頁(yè)
文件大?。?/td> 1207K
代理商： CL-PS7111
September 1997
63
PRELIMINARY DATA BOOK v2.0
REGISTER DESCRIPTIONS
CL-PS7111
Low-Power System-on-a-Chip
5.19
Pump Control Register — PMPCON
The DC-to-DC Converter Pump Control register is a 12-bit read/write-only register that sets and controls
the variable mark space ratio drives for two DC-to-DC converters. All bits in this register are cleared by a
system reset.
11:8
7:4
3:0
Drive 1 pump ratio
Drive 0 from mains ratio
Drive 0 from battery ratio
Bit
Description
3:0
Drive 0 from Battery:
This 4-bit field controls the on time for the drive 0 DC-to-DC pump while the system is pow-
ered from batteries. Setting these bits to ‘0’ disables this pump, setting these bits to ‘1’ allows the pump to be
driven in a 1:16 duty ratio, 2 in a 2:16 duty ratio, etc., up to a 15:16 duty ratio. An 8:16 duty ratio results in a square
wave of 96 kHz when operating with an 18.432-MHz master clock, or 101.6 kHz when operating from the 13-MHz
source. The NEXTPWR input is used to switch between the two on times for ‘drive0’.
7:4
Drive 0 from Mains:
This 4-bit field controls the on time for the drive 0 DC-to-DC pump while the system is pow-
ered from mains. Setting these bits to ‘0’ disables this pump; setting these bits to ‘1’ allows the pump to be driven
in a 1:16 duty ratio, 2 in a 2:16 duty ratio, etc., up to a 15:16 duty ratio. An 8:16 duty ratio results in a square wave
of 96 kHz when operating with an 18.432-MHz master clock, or 101.6 kHz when operating from the 13-MHz
source. The NEXTPWR input switches between the two on times for ‘drive 0’.
11:8
Drive 1 Pump Ratio:
This 4-bit field controls the on time for the drive 1 DC-to-DC pump. Setting these bits to ‘0’
disables this pump, setting these bits to ‘1’ allows the pump to be driven in a 1:16 duty ratio, 2 in a 2:16 duty ratio,
etc., up to a 15:16 duty ratio. An 8:16 duty ratio results in a square wave of 96 kHz when operating with an
18.432-MHz master clock, or 101.6 kHz when operating from the 13-MHz source.
The state of the output drive pins is latched during power-on reset, this latched value is used to determine the
polarity of the drive output. The sense of the DC-to-DC converter control lines is summarized in the following table.
Initial State of Drive ‘n’ during
POR
Sense of Drive ‘n’
Polarity of Bias Voltage
Low
Active high
+VE
High
Active low
-VE
相關(guān)PDF資料
PDF描述
CL-PS7111-VC-A Low-Power System-on-a-Chip
CL-PS7500FE System-on-a Chip for Internet Appliance
CL-SH8665 Integrated ATA Drive microcontroller(集成ATA驅(qū)動(dòng)微控制器)
CL1431 Precision Adjustable Shunt Reference
CL1431D Precision Adjustable Shunt Reference
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CL-PS7111(208LQFP) 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Logic IC
CL-PS7111(256PBGA) 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Logic IC
CL-PS7111-VC-A 制造商:CIRRUS 制造商全稱(chēng):Cirrus Logic 功能描述:Low-Power System-on-a-Chip
CL-PS7500FE 制造商:CIRRUS 制造商全稱(chēng):Cirrus Logic 功能描述:System-on-a Chip for Internet Appliance
CLPT-12SP-06 制造商:Tri-Star Electronics International 功能描述:CONNECTOR - Bulk
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*