參數(shù)資料
型號: CL-PS7111
廠商: Cirrus Logic, Inc.
英文描述: Low-Power System-on-a-Chip
中文描述: 低功耗系統(tǒng)級晶片
文件頁數(shù): 78/105頁
文件大?。?/td> 1207K
代理商: CL-PS7111
September 1997
77
PRELIMINARY DATA BOOK v2.0
ELECTRICAL SPECIFICATIONS
CL-PS7111
Low-Power System-on-a-Chip
Figure 6-1. Expansion and ROM Read Timing
NOTES:
1)
t
EXRD
= maximum 70 ns and 120 ns for minimum wait states and a main oscillator frequency of 18.432 MHz
and 13.0 MHz respectively. This time can be extended by integer multiples of the clock period (54 ns), by
either driving EXPRDY low and or by programming a number of wait states. EXPRDY is sampled on the falling
edge of EXPCLK before the data transfer; if low at this point, the transfer is delayed by one clock period where
EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY but is shown for clarity.
2)
Consecutive reads with sequential access enabled are identical except that the sequential access wait state
field is used to determine the number of wait states, and no idle cycles are inserted between successive non
sequential ROM/expansion cycles. This improves performance, so the SQAEN should always be set where
possible.
EXPCLK
BUS HELD
t
5
t
1
t
6
t
4
t
3
NMOE
A[27:0]
D[31:0]
DATA IN
DATA IN
WORD
NCS[5:0]
EXPRDY
t
ADRD
t
PCSRD
t
3
t
4
Consecutive expansion read cycles with minimum wait states
t
NCSRD
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