參數(shù)資料
型號(hào)： CL-PS7111
廠商： Cirrus Logic, Inc.
英文描述： Low-Power System-on-a-Chip
中文描述： 低功耗系統(tǒng)級(jí)晶片
文件頁(yè)數(shù)： 39/105頁(yè)
文件大?。?/td> 1207K
代理商： CL-PS7111
PRELIMINARY DATA BOOK v2.0
September 1997
38
FUNCTIONAL DESCRIPTION
CL-PS7111
Low-Power System-on-a-Chip
3.13.1
Interrupt Latencies in Different States
Normal Operating States
The ARM710a macrocell checks for a low level on its FIQ/IRQ inputs at the end of each instruction. First,
there is a one- or two-clock cycle synchronization penalty. For the case where the CL-PS7111 is operating
at 13 MHz with a 16-bit external memory system and instruction sequence stored in one-wait-state flash
memory, the worst-case interrupt latency is 251 clock cycles. This corresponds to the ARM executing an
STM instruction in DRAM, and the MMU needs to fetch protection/translation information from page
tables in DRAM memory. This also includes a delay for cache linefills for instruction prefetches, a data
abort occurring at the end of the LDM, and the LDM being non-quad word aligned. In addition, the worst-
case interrupt latency assumes that LCD DMA cycles support a panel size of 320 by 240 at 4 bits per pixel
and a 60-Hz refresh rate.
This would give a worst-case interrupt latency of about 19.3
μ
s for the ARM710a macrocell operating at
13 MHz. For those interrupt inputs with error correction, this figure is increased by the maximum time
required to pass through the deglitcher, which is approximately 60
μ
s (1 cycle of the 16.384-kHz clock
derived from the RTC oscillator). So the absolute worst case latency is approximately 80
μ
s.
All the serial data transfer peripherals included in CL-PS7111 (except for the master-only SSI) have local
buffering to ensure a reasonable interrupt latency response requirement for the O/S of 1 ms or less,
assuming that the maximum data rates described in this specification are complied with. If the O/S cannot
meet this requirement, then there will be a risk of data overflow/underflow occurring.
Idle State
When leaving idle mode as a result of an interrupt, the CPU clock is restarted after approximately two
clock cycles. However, there is still potentially up to 20-
μ
s latency as described above, unless the code is
written to include at least two single cycle instructions immediately after the write to the IDLE register (in
which case the latency drops to a few microseconds). This is important because idle mode will have been
left as a result of a pending interrupt, which has to be synchronized by the ARM before it can be serviced.
Standby State
In standby mode, the latency time will depend on whether the system clock is shut down. If running at
18.432 MHz, then the PLL will always be shut down in standby mode in which case there will be a latency
time of 0.125 to 0.25 sec. If the system is running at 13 MHz with the CLKENSL bit in SYSCON2 set to
0, then the latency will also be between 0.125 and 0.25 sec. to enable an external oscillator to stabilize.
In the case of a 13-MHz system where the clock is not disabled during standby (CLKENSL = 1), then the
latency will be less than 1
μ
s if single-cycle instructions are used after the write to the standby location.
Table 3-13. Interrupt Allocation in Second Interrupt Register Set
Interrupt
Bit in INTMR2
and INTSR2
Name
Comment
IRQ
0
KBDINT
Key press interrupt
IRQ
12
UTXINT2
Internal UART2 transmit FIFO empty interrupt.
IRQ
13
URXINT2
Internal UART2 receive FIFO full interrupt.
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