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參數(shù)資料
| 型號(hào)： | CL-PS7111 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | Low-Power System-on-a-Chip |
| 中文描述： | 低功耗系統(tǒng)級(jí)晶片 |
| 文件頁數(shù)： | 52/105頁 |
| 文件大?。?/td> | 1207K |
| 代理商： | CL-PS7111 |
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September 1997
51
PRELIMINARY DATA BOOK v2.0
REGISTER DESCRIPTIONS
CL-PS7111
Low-Power System-on-a-Chip
28:27
BOOTBIT0–1:
These bits indicate the default (power-on reset) bus width of the ROM interface. See the Memory Con-
figuration registers on
page 53
for more details on the ROM interface bus width. The state of these bits reflects the
state of Port E bits 0–1 during power-on reset, as shown in the following table:
26
SSIBUSY:
Synchronous serial interface busy. This bit is set while data is shofted in or out of the seynchronous serial
interface. When this bit is clear, data is valid for reads.
25
CTXFF:
Codec Tx FIFO full bit. This is set if the 16-byte codec Tx FIFO is full.
24
CRXFE:
Codec Rx FIFO empty bit. This is set if the 16-byte codec Rx FIFO is empty.
23
UTXFF1:
UART1 transmit FIFO full. The meaning of this bit depends on the state of the UFIFOEN bit in the UART1 Bit
Rate and Line Control register. If the FIFO is disabled, this bit is set when the Tx Holding register is full. If the FIFO is
enabled, the UTXFF1 bit is set when the Tx FIFO is full.
22
URXFE1:
UART1 receiver FIFO empty. The meaning of this bit depends on the state of the UFIFOEN bit in the UART1
Bit Rate and Line Control register. If the FIFO is disabled, this bit is set when the Rx Holding register is empty. If the
FIFO is enabled the URXFE bit is set when the Rx FIFO is empty.
21:16
RTCDIV:
This 6-bit field reflects the number of 64-Hz ticks that have passed since the last increment of the RTC. It is
the output of the divide-by-64 chain that divides the 64-Hz tick clock down to 1 Hz for the RTC. The MSB is the 32-Hz
output; the LSB is the 1-Hz output.
15
CLDFLG:
Cold start flag. This bit is set if the CL-PS7111 has been reset with a power on reset; it is cleared by writing
to the STFCLR location.
14
PFFLG:
Power fail flag. This bit is set if the system has been reset by the power fail input pin, it is cleared by writing to
the STFCLR location.
13
RSTFLG:
Reset flag. This bit is set if the RESET button is pressed, forcing the NURESET input low. It is cleared by
writing to the STFCLR location.
12
NBFLG:
New battery flag. This bit is set if a low-to-high transition has occurred on the NBATCHG input; it is cleared by
writing to the STFCLR location.
11
UBUSY1:
UART1 transmitter busy. This bit is set while the UART1 is busy transmitting data; it is guaranteed to remain
set until the complete byte has been sent, including all stop bits.
10
DCD:
This bit reflects the current status of the data carrier detect (DCD) modem-control input to the UART1.
9
DSR:
This bit reflects the current status of the data set ready (DSR) modem-control input to the UART1.
8
CTS:
This bit reflects the current status of the clear to send (CTS) modem-control input to the UART1.
Bit
Description
(cont.)
PE1 (BOOTBIT1)
PE0 (BOOTBIT0)
Boot Option
0
0
32 bit
0
1
8 bit
1
0
16 bit
1
1
Reserved
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CL-PS7111-VC-A | Low-Power System-on-a-Chip |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CL-PS7111(208LQFP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| CL-PS7111(256PBGA) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| CL-PS7111-VC-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-Power System-on-a-Chip |
| CL-PS7500FE | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:System-on-a Chip for Internet Appliance |
| CLPT-12SP-06 | 制造商:Tri-Star Electronics International 功能描述:CONNECTOR - Bulk |
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