參數(shù)資料
型號(hào): CL-PS7111
廠商: Cirrus Logic, Inc.
英文描述: Low-Power System-on-a-Chip
中文描述: 低功耗系統(tǒng)級(jí)晶片
文件頁(yè)數(shù): 58/105頁(yè)
文件大?。?/td> 1207K
代理商: CL-PS7111
September 1997
57
PRELIMINARY DATA BOOK v2.0
REGISTER DESCRIPTIONS
CL-PS7111
Low-Power System-on-a-Chip
5.11
DRAM Refresh Period Register — DRFPR
The DRAM Refresh Period register is an 8-bit read/write register that enables refresh and selects the
refresh period used by the DRAM controller for its periodic CAS-before-RAS refresh. The value in the
DRAM refresh period register is only
cleared by a power on reset, that is, the register state is maintained
during a power fail or user reset.
7
6
5
4
3
2
1
0
RFSHEN
RFDIV
Bit
Description
7
RFSHEN:
DRAM refresh enable. Setting this bit enables periodic refresh cycles to be generated by the CL-PS7111 at
a rate set by the RFDIV field. Setting this bit also enables Self-refresh mode when the CL-PS7111 is in the standby
state.
6:0
RFDIV:
This 7-bit field sets the DRAM refresh rate. The refresh period is derived from a 128-kHz clock as shown in
Equation 5-1
.
Frequency (kHz) = 128/(RFDIV + 1), that is,
RFDIV = (128/Refresh frequency (kHz))
1
Equation 5-1
This equation is valid for both 13-MHz and 18-MHz modes. The equation for frequency gives the refresh rate for the
DRAM.
The maximum refresh frequency is 64 kHz, the minimum is 1 kHz. The RFDIV field should not be programmed with ‘0’
as this results in no refresh cycles being initiated. These values are valid for both 13-MHz and 18-MHz modes of oper-
ation.
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