參數(shù)資料
型號(hào)： CL-PS7111
廠商： Cirrus Logic, Inc.
英文描述： Low-Power System-on-a-Chip
中文描述： 低功耗系統(tǒng)級(jí)晶片
文件頁(yè)數(shù)： 49/105頁(yè)
文件大?。?/td> 1207K
代理商： CL-PS7111
PRELIMINARY DATA BOOK v2.0
September 1997
48
REGISTER DESCRIPTIONS
CL-PS7111
Low-Power System-on-a-Chip
5.8.1
System Control Register 1 — SYSCON1
The System Control register is a 21-bit read/write register that controls the general configuration of the
CL-PS7111 as well as modes for peripheral devices. All bits in this register are cleared by a system reset.
23
22
21
20
19
18
17
16
1
Reserved
IRTXM
WAKEDIS
EXCKEN
ADCKSEL
15
14
13
12
11
10
9
8
SIREN
CDENRX
CDENTX
LCDEN
DBGEN
BZMOD
BZTOG
UART1EN
7
6
5
4
3
2
1
0
TC2S
TC2M
TC1S
TC1M
Keyboard Scan
Bit
Description
23
This bit must always be set to ‘1’.
22:21
Reserved
20
IRTXM:
IrDA Tx mode bit. This bit controls the IrDA encoding strategy. Clearing this bit means each ‘0’ bit transmitted
is represented as a pulse of width 3/16th of the bit rate period. Setting this bit means each ‘0’ bit is represented as a
pulse of width 3/16th of the period of 115,200 bit rate clock, that is, 1.6
μ
s, regardless of the selected bit rate. Setting
this bit reduces power consumption, but probably reduces transmission distances.
19
WAKEDIS:
Setting this bit disables wake-up from standby mode through the WAKEUP + KBD inputs.
18
EXCKEN:
External expansion clock enable. If this bit is set, the EXPCLK is enabled continuously; it is the same speed
and phase as the CPU clock, and free-run all the time the main oscillator is running. Do not leave this bit set for power
consumption reasons. If the system enters the standby state, the EXPCLK is undefined. If this bit is clear, EXPCLK is
active during memory cycles only to the expansion slots that have external wait-state generation enabled.
17:16
ADCKSEL:
Microwire
/SPI
peripheral clock speed select. This 2-bit field selects the frequency of the ADC sample
clock, which is twice the frequency of the synchronous serial ADC interface clock. The following table shows the avail-
able frequencies, assuming operation at 18.432-MHz mode. The frequencies obtained at 13-MHz mode can be found
on
Table 3-17 on page 41
.
15
SIREN:
HP SIR protocol encoding enable. If the UART is not enabled, this bit has no effect.
Bit
ADC Sample Frequency (kHz)
SMPCLK
ADC interface frequency (kHz) —
ADCCLK
17
16
0
0
8
4
0
1
32
16
1
0
128
64
1
1
256
128
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