參數(shù)資料
型號: CL-PS7111
廠商: Cirrus Logic, Inc.
英文描述: Low-Power System-on-a-Chip
中文描述: 低功耗系統(tǒng)級晶片
文件頁數(shù): 59/105頁
文件大?。?/td> 1207K
代理商: CL-PS7111
PRELIMINARY DATA BOOK v2.0
September 1997
58
REGISTER DESCRIPTIONS
CL-PS7111
Low-Power System-on-a-Chip
5.12
Interrupt Status Register 1 — INTSR1
The Interrupt Status register is a 32-bit read-only register. This register reflects the current state of the
first 16 interrupt sources within the CL-PS7111. Each bit is set if the appropriate interrupt is active. The
following describes the interrupt assignments.
15
14
13
12
11
10
9
8
SSEOTI
UMSINT
URXINT1
UTXINT
TINT
RTCMI
TC2OI
TC1OI
7
6
5
4
3
2
1
0
EINT3
EINT2
EINT1
CSINT
MCINT
WEINT
BLINT
EXTFIQ
Bit
Description
15
SSEOTI:
Synchronous serial interface end-of-transfer interrupt. This interrupt is active after a complete data transfer to
and from the external ADC has completed. It is cleared by reading the ADC data from the SYNCIO register.
14
UMSINT:
Internal UART1 modem status changed interrupt. This interrupt is active if either of the two modem status
lines (CTS or DSR) change state. It is cleared by writing to the UMSEOI location.
13
URXINT:
Internal UART1 receive FIFO half-full interrupt. The function of this interrupt source depends on whether the
UART1 FIFO is enabled. If the FIFO is disabled this interrupt is active when there is valid Rx data in the UART1 Rx
Data Holding register, and is cleared by reading this data. If the FIFO is enabled this interrupt is active when the
UART1 Rx FIFO is half or more full or if the FIFO is non empty and no more characters are received for a 3-character
time-out period. It is cleared by reading all the data from the Rx FIFO.
12
UTXINT1:
Internal UART1 transmit FIFO half-empty interrupt. The function of this interrupt source depends on whether
the UART1 FIFO is enabled. If the FIFO is disabled (FIFOEN bit is clear in the UART1 Bit Rate and Line Control regis-
ter), this interrupt is active when there is no data in the UART1 Tx Data Holding register, and cleared by writing to the
UART1 Data register. If the FIFO is enabled this interrupt is active when the UART1 Tx FIFO is half or more empty, and
is cleared by filling the FIFO to at least half full.
11
TINT:
64-Hz tick interrupt. This interrupt becomes active on every rising edge of the internal 64-Hz clock signal. This
64-Hz clock is derived from the 15-stage ripple counter that divides the 32.768-kHz oscillator input down to 1 Hz for the
realtime clock. This interrupt is cleared by writing to the TEOI location.
10
RTCMI:
RTC compare match interrupt. This interrupt becomes active on the
next
rising edge of the 1-Hz realtime
clock (one second later) after the 32-bit time written to the realtime clock match register exactly matches the current
time in the RTC. It is cleared by writing to the RTCEOI location.
9
TC2OI:
TC2 under-flow interrupt. This interrupt becomes active on the
next
falling edge of the timer counter 2 clock
after the timer counter has under-flowed (reached ‘0’). It is cleared by writing to the TC2EOI location.
8
TC1OI:
TC1 under-flow interrupt. This interrupt becomes active on the
next
falling edge of the timer counter 1 clock
after the timer counter has under-flowed (reached ‘0’). It is cleared by writing to the TC1EOI location.
7
EINT3:
External interrupt input 3. This interrupt is active if the EINT3 input is active (high) it is cleared by returning
EINT3 to the passive (low) state.
6
EINT2:
External interrupt input 2. This interrupt is active if the NEINT2 input is active (low). It is cleared by returning
NEINT2 to the passive (high) state.
5
EINT1:
External interrupt input 1. This interrupt is active if the NEINT1 input is active (low). It is cleared by returning
NEINT1 to the passive (high) state.
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