參數(shù)資料
型號(hào)： CL-PS7111
廠商： Cirrus Logic, Inc.
英文描述： Low-Power System-on-a-Chip
中文描述： 低功耗系統(tǒng)級(jí)晶片
文件頁(yè)數(shù)： 38/105頁(yè)
文件大?。?/td> 1207K
代理商： CL-PS7111
September 1997
37
PRELIMINARY DATA BOOK v2.0
FUNCTIONAL DESCRIPTION
CL-PS7111
Low-Power System-on-a-Chip
3.13
Interrupt Controller
The ARM710a has two interrupt types: IRQ (interrupt request) and FIQ (fast interrupt request). The inter-
rupt controller in the CL-PS7111 controls interrupts from 23 different sources. Nineteen interrupt sources
are mapped to the IRQ input and four sources are mapped to the FIQ input. FIQs have a higher priority
than IRQs: if two interrupts within the same group (IRQ or FIQ) are active, software must resolve the order
in which they are serviced.
All interrupts are level-sensitive hat is, they must conform to the following sequence:
1)
The device asserts the appropriate interrupt request line.
2)
If the appropriate bit is set in the Interrupt Mask register, either FIQ or IRQ is asserted by the interrupt con-
troller.
3)
If interrupts are enabled, the processor jumps to the appropriate address.
4)
Interrupt dispatch software reads the Interrupt Status register to establish the source(s) of the interrupt, and
then calls the appropriate interrupt service routine(s).
5)
Software in the interrupt service routine clears the interrupt source by some action specific to the device
requesting the interrupt (for example, reading the UART Rx register).
6)
The interrupt service routine can then re-enable interrupts. Any other pending interrupts are serviced in a
similar way or returned to the interrupt dispatch code, which checks for any more pending interrupts and dis-
patches them accordingly.
Table 3-12
and
Table 3-13
show the names and allocation of interrupts in CL-PS7111. For more informa-
tion, see
Section 5.12 on page 58
.
Table 3-12. Interrupt Allocation in First Interrupt Register Set
Interrupt
Bit in INTMR1
and INTSR1
Name
Comment
FIQ
0
EXTFIQ
External fast interrupt input (NEXTFIQ pin).
FIQ
1
BLINT
Battery low interrupt.
FIQ
2
WEINT
Watch dog expired interrupt.
FIQ
3
MCINT
Media changed interrupt.
IRQ
4
CSINT
Codec sound interrupt.
IRQ
5
EINT1
External interrupt input 1 (NEINT1 pin).
IRQ
6
EINT2
External interrupt input 2 (NEINT2 pin).
IRQ
7
EINT3
External interrupt input 3 (EINT3 pin).
IRQ
8
TC1OI
TC1 under flow interrupt.
IRQ
9
TC2OI
TC2 under flow interrupt.
IRQ
10
RTCMI
RTC compare match interrupt.
IRQ
11
TINT
64-Hz tick interrupt.
IRQ
12
UTXINT1
Internal UART1 transmit FIFO empty interrupt.
IRQ
13
URXINT1
Internal UART1 receive FIFO full interrupt.
IRQ
14
UMSINT
Internal UART1 modem status changed interrupt.
IRQ
15
SSEOTI
Synchronous serial interface, end of transfer interrupt.
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