
September 1997
13
PRELIMINARY DATA BOOK v2.0
PIN INFORMATION
CL-PS7111
Low-Power System-on-a-Chip
54
PD[6]
I/O - strength 1
Low
80
FB[1]
Input
55
PD[5]
I/O - strength 1
Low
81
VSS
I/O - strength 1
Input
56
PD[4]
I/O - strength 1
Low
82
FB[0]
I/O - strength 1
Input
57
VDD
Pad power
–
83
COL[7]/
PTOUT
I/O - strength 1
High
58
VSS
Pad power
–
84
COL[6]
I/O - strength 1
High
59
PD[3]
I/O - strength 1
Low
85
COL[5]
I/O - strength 0
b
High
60
PD[2]
I/O - strength 1
Low
86
COL[4]
I/O - strength 1
High
61
PD[1]
I/O - strength 1
Low
87
COL[3]
I/O - strength 1
High
62
PD[0]
I/O - strength 1
Low
88
COL[2]
I/O - strength 1
High
63
PCMCLK
–
Input
89
VDD
Pad power
–
64
VSS
Core power
–
90
VSS
Pad power
–
65
PCMSYNC
I/O - strength 1
Low
91
COL[1]
I/O - strength 1
High
66
PCMOUT
I/O - strength 1
Low
92
COL[0]
I/O - strength 1
High
67
PCMIN
I/O - strength 1
Input
93
BUZ
I/O - strength 1
Low
68
N/C
I/O - strength 1
Low
94
D[31]
I/O - strength 1
Low
69
ADCIN
I/O - strength 1
Input
95
D[30]
I/O - strength 1
Low
70
NADCCS
I/O - strength 1
High
96
D[29]
I/O - strength 1
Low
71
VSS
Core power
–
97
D[28]
I/O - strength 1
Low
72
VDD
Core power
–
98
VSS
–
73
VSS
Pad power
–
99
A[27]/DRA[0]
I/O - strength 2
Low
74
VDD
Pad power
–
100
D[27]
I/O - strength 1
Low
75
DRIVE[1]
I/O - strength 3
High/Low
101
A[26]/DRA[1]
I/O - strength 2
Low
76
DRIVE[0]
I/O - strength 3
High/Low
102
D[26]
I/O - strength 1
Low
77
ADCCLK
I/O - strength 1
Low
103
A[25]/DRA[2]
I/O - strength 1
Low
78
ADCOUT
I/O - strength 1
Low
104
D[25]
I/O - strength 1
Low
77
ADCCLK
I/O - strength 1
Low
105
N/C
78
ADCOUT
I/O - strength 1
Low
106
A[24]/DRA[3]
I/O - strength 1
Low
107
VDD
Pad power
–
136
A[12]
I/O - strength 1
Low
108
VSS
Pad power
–
137
D[12]
I/O - strength 1
Low
2.2.2
Numeric Pin Listing
(cont.)
Pin
No.
Signal
Buffer
Reset and
Pin Test
Reset State
Pin
No.
Signal
Buffer
Reset and
Pin Test
Reset State