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參數(shù)資料
| 型號： | CL-PS7111 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | Low-Power System-on-a-Chip |
| 中文描述： | 低功耗系統(tǒng)級晶片 |
| 文件頁數(shù)： | 72/105頁 |
| 文件大?。?/td> | 1207K |
| 代理商： | CL-PS7111 |
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September 1997
71
PRELIMINARY DATA BOOK v2.0
REGISTER DESCRIPTIONS
CL-PS7111
Low-Power System-on-a-Chip
5.39
System Status Flags Register 2 — SYSFLG2
This register is an extension of SYSFLG1, containing status bits for the features new to the CL-PS7111.
2
DRAMSZ:
Determines width of DRAM memory interface, where 0 = 32-bit DRAM bank; 1 = 16-bit DRAM bank
1
KBD6:
The state of this bit determines how many Port A inputs are OR’ed together to create the keyboard interrupt
(and the internal WAKEUP signal if this functionality is enabled by the KBWEN bit). When ‘0’ (the reset state), all 8 Port
A inputs generate a keyboard interrupt. When set high, only Port A bits 0 to 5 generate an interrupt from the keyboard.
It is assumed that the keyboard row lines are connected into Port A.
0
CODECEN:
This bit must always be set to ‘1’.
23
22
21
20
19
18
17
16
UTXFF2
URXFE2
Reserved
15
14
13
12
11
10
9
8
Reserved
UBUSY2
Reserved
7
6
5
4
3
2
1
0
Reserved
CKMODE
Reserved
Bit
Description
23
UTXFF2:
UART2 transmit FIFO full. The meaning of this bit depends on the state of the UFIFOEN bit in the UART2 bit
rate and line control register. If the FIFO is disabled, this bit is set when the Tx holding register is full. If the FIFO is
enabled, the UTXFF bit is set when the Tx FIFO is full.
22
URXFE2:
UART2 receiver FIFO empty. The meaning of this bit depends on the state of the UFIFOEN bit in the UART2
bit rate and line control register. If the FIFO is disabled, this bit is set when the Rx holding register contains is empty. If
the FIFO is enabled the URXFE bit is set when the Rx FIFO is empty.
21:12
Reserved
11
UBUSY2:
UART2 transmitter busy. This bit is set while UART2 is busy transmitting data. It is guaranteed to remain set
until the complete byte has been sent, including all stop bits.
10:7
Reserved
6
CKMODE:
This bit reflects the status of the CLKSEL (Port E bit 2) input, latched during NPOR. When low, the PLL is
running and the chip is operating in 18.432-MHz mode. When high, the chip is operating from an external 13-MHz
clock.
5:0
Reserved
Bit
Description
(cont.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CL-PS7111-VC-A | Low-Power System-on-a-Chip |
| CL-PS7500FE | System-on-a Chip for Internet Appliance |
| CL-SH8665 | Integrated ATA Drive microcontroller(集成ATA驅(qū)動微控制器) |
| CL1431 | Precision Adjustable Shunt Reference |
| CL1431D | Precision Adjustable Shunt Reference |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CL-PS7111(208LQFP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| CL-PS7111(256PBGA) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| CL-PS7111-VC-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-Power System-on-a-Chip |
| CL-PS7500FE | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:System-on-a Chip for Internet Appliance |
| CLPT-12SP-06 | 制造商:Tri-Star Electronics International 功能描述:CONNECTOR - Bulk |
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