參數(shù)資料
型號(hào)： CL-PS7111
廠商： Cirrus Logic, Inc.
英文描述： Low-Power System-on-a-Chip
中文描述： 低功耗系統(tǒng)級(jí)晶片
文件頁(yè)數(shù)： 71/105頁(yè)
文件大小： 1207K
代理商： CL-PS7111
PRELIMINARY DATA BOOK v2.0
September 1997
70
REGISTER DESCRIPTIONS
CL-PS7111
Low-Power System-on-a-Chip
5.37
LCD Frame Buffer Start Address — FRBADDR
This register contains the start address for the LCD Frame Buffer. (It is assumed that the frame buffer
starts at location 0x0000000 within each chip-select memory region; therefore the value stored within the
FRBADDR is only the value of the chip select where the frame buffer is located.) On reset, this is set to
0xC for backward compatibility with CL-PS7110. The register is 4 bits wide. This register must only be
reprogrammed while the LCD is disabled (that is, setting low the LCDEN bit within SYSCON2).
5.38
System Control Register 2 — SYSCON2
This register is an extension of SYSCON1, containing control bits for the features which are new for
CL-PS7111. The bits of the second system control register are defined as shown in the above bit descrip-
tion table.
15
14
13
12
11
10
9
8
Reserved
BUZFREQ
CLKENSL
OSTB
Reserved
Reserved
Reserved
UART2EN
7
6
5
4
3
2
1
0
Reserved
PCMCIA2
PCMCIA1
Reserved
KBWEN
DRAMSZ
KBD6
CODECEN
Bit
Description
15
Reserved
14
BUZFREQ:
BUZ output select. When low, the buzzer signal generated from the on-chip timer is output. When high, a
fixed-frequency clock is output (500 Hz in 18.432-MHz mode and 528 Hz in 13-MHz mode).
13
CLKENSL:
Clock enable select. When low, the CLKEN signal is output on the RUN/CLKEN pin. When high, the run
signal is output on RUN/CLKEN.
12
OSTB:
This operating system timing bit is for use only with the 13-MHz operating mode. Normally it is set low; how-
ever, when set high it causes a 500-kHz clock to be generated for the timers instead of the 541-kHz one that would
normally be available. The divider to generate this frequency is not clocked when this bit is set low.
11:9
Reserved
8
UART2EN:
Internal UART2 enable bit. Setting this bit enables the internal UART2.
7
Reserved
6
PCMCIA2:
Enables the interface to the CL-PS6700 device for PCMCIA slot 2. The main effect of this bit is to reassign
the functionality of Port B bit 1 to the PRDY input from the CL-PS6700 devices, and to ensure that any access to the
NCS4 address space is according to the CL-PS6700 interface protocol.
5
PCMCIA1:
Enables the interface to the CL-PS6700 device for PCMCIA slot 1. The main effect of this bit is to reassign
the functionality of Port B bit 0 to the PRDY input from the CL-PS6700 devices, and to ensure that any access to the
NCS4 address space is according to the CL-PS6700 interface protocol.
4
Reserved
3
KBWEN:
When set high, this bit enables the functionality that allows the CL-PS7111 to wake up from a power saving
state into the operating state from Port A, irrespective of the status of the Interrupt Mask register.
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