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參數(shù)資料
| 型號(hào)： | ADT7462ACPZ-500RL7 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 4Cel, SQUARE, SURFACE MOUNT |
| 封裝： | 5 X 5 MM, LFCSP-32 |
| 文件頁數(shù)： | 9/88頁 |
| 文件大?。?/td> | 836K |
| 代理商： | ADT7462ACPZ-500RL7 |
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ADT7462
Rev. 2 | Page 17 of 88 | www.onsemi.com
SERIAL BUS INTERFACE
The ADT7462 is controlled through use of the serial system
management bus (SMBus). The ADT7462 is connected to this
bus as a slave device, under the control of a master controller.
The SMBus interface in the ADT7462 is fully SMBus 1.1 and
SMBus 1.0 compliant. The SMBus address is determined by the
state of the ADD input on power-up.
ADD INPUT
The ADD pin is a three-state input to the ADT7462. It is used
to determine the SMBus address used. This pin is sampled on
power-up only. Any changes subsequent to power-up are not
reflected until the ADT7462 is powered down and back up
again. The corresponding 7-bit SMBus address for the state of
the ADD pin is shown in Table 11.
Table 11. Corresponding SMBus Addresses for ADD Input
ADD Pin
SMBus Version
SMBus Address
High
N/A
Float
SMBus 1.1
0x5C
Low
SMBus 1.1
0x58
SMBus FIXED ADDRESS
The ADT7462 supports SMBus fixed address mode and is fully
backward compatible with SMBus 1.1 and SMBus 1.0. The
ADT7462 powers up with a fixed SMBus address that cannot
be changed by the assign address call. The fixed address is set
by the state of the ADD input pin on power-up. The ADT7462 also
responds to the SMBus device default address of 0x61.
SMBus OPERATION
The SMBus specification defines specific conditions for different
types of read and write operations. The general SMBus protocol
operates as follows:
1.
The master initiates data transfer by establishing a start condi-
tion, defined as a high-to-low transition on the serial data
line, SDA, while the serial clock line, SCL, remains high. This
indicates that an address/data stream follows. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next eight bits, consisting of a
7-bit address (MSB first) plus a R/W bit, which determines
the direction of the data transfer, that is, whether data is
written to or read from the slave device.
2.
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the
low period before the 9th clock pulse, known as the
acknowledge bit. All other devices on the bus remain idle
while the selected device waits for data to be read from it or
written to it. If the R/W bit = 0, the master writes to the
slave device. If the R/W bit = 1, the master reads from the
slave device.
3.
Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, because a low-to-high
transition when the clock is high can be interpreted as
a stop signal. The number of data bytes that can be
transmitted over the serial bus in a single read or write
operation is limited only by what the master and slave
devices can handle.
4.
When all data bytes have been read or written, stop
conditions are established. In write mode, the master releases
the data line during the 10th clock pulse to assert a stop
condition. In read mode, the master device overrides the
acknowledge bit by pulling the data line high during the
low period before the 9th clock pulse. This is known as a
no acknowledge. The master then takes the data line low
during the low period before the 10th clock pulse and then
takes it high during the 10th clock pulse to assert a stop
condition.
Any number of bytes of data can be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
For the ADT7462, write operations contain either one or two
bytes, and read operations contain one byte. To write data to
one of the device data registers or to read data from it, the
address pointer register must be set so that the correct data
register is addressed. Then data can be written into that register
or read from it. The first byte of a write operation always con-
tains an address that is stored in the address pointer register. If
data is to be written to the device, the write operation contains
a second data byte that is written to the register selected by the
address pointer register.
This write operation is shown in Figure 25. The device address
is sent over the bus, and then R/W is set to 0. This is followed
by two data bytes. The first data byte is the address of the
internal data register to be written to, which is stored in the
address pointer register. The second data byte is the data to be
written to the internal data register.
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